In mid-August, Samsung is said to be accelerating its progress on next-gen HBM, targeting to tape-out HBM4 by the end of this year. Now it seems SK hynix has maintained its competitive edge, as the company aims to tape out HBM4 in October, which will be used to power NVIDIA’s Rubin AI chips, according to the reports by Wccftech and ZDNet.

In addition, the reports note that SK hynix also plans to tape out HBM4 for AMD’s AI chips, which is expected to take place a few month later.

To further prepare for the strong demand from AI chip giants’ upcoming product launch, SK hynix is assembling development teams to supply HBM4 to NVIDIA and AMD, according to Wccftech and ZDNet.

Per SK hynix’s product roadmap, the company plans to launch 12-layer stacked HBM4 in the second half of 2025 and 16-layer in 2026. With NVIDIA’s Rubin series planned for 2026, it is expected to adopt HBM4 12Hi with 8 clusters per GPU.

SK hynix is the major HBM3e supplier for NVIDIA’s AI chips, as the memory giant has taken the lead by starting shipping the product a few months ago, followed by Micron. Samsung’s HBM3, on the other hand, have been cleared by NVIDIA in July, while its HBM3e is still striving to pass NVIDIA’s qualification.

According to the reports, the introduction of HBM4 represents another major milestone for SK hynix, as it offers the fastest DRAM with exceptional power efficiency and higher bandwidth.

HBM4 will feature double the channel width of HBM3E, offering 2048 bits versus 1024 bits. Moreover, it supports stacking 16 DRAM dies, up from 12 in HBM3e, with options for 24Gb and 32Gb layers. This advancement will enable a capacity of 64GB per stack, compared to 32GB with HBM3e, the reports suggest.

On August 19, SK hynix showcased the ambition on securing its leadership on HBM, claiming that the company is developing a product with performance up to 30 times higher than current HBM.

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(Photo credit: SK hynix)

Amid the AI boom driving a surge in demand for advanced packaging, Samsung Electronics announced in March its ambition to achieve record-high revenue for the business this year, aiming to surpass the USD 100 million mark. The company, which is eager to catch up with TSMC not only on the foundry but also the advanced packaging business, was said to hire former TSMC deputy director Vic Lin as Vice President of the Advanced Packaging Business Unit in its semiconductor department. However, according to a report by ijiwei, the business unit has been disbanded recently, and rumor has it that Chinese semiconductor companies are attempting to recruit Lin.

It is worth noting that before joining TSMC, Lin worked at Micron Technology. Afterwards, during his 19-year tenure at TSMC from 1999 to 2017, Lin was responsible for the application of the semiconductor giant’s over 450 U.S. patents, the report notes. His major accomplishments included securing a major collaboration deal with Apple, as well as laying a solid foundation for TSMC’s expertise in 3D packaging technology.

Nowadays, the advanced packaging business has emerged as one of TSMC’s major growth momentum, with primary customer NVIDIA having the highest demand, occupying about half of the capacity, followed closely by AMD. As the demands for AI and HPC processors keep booming, TSMC revealed plans earlier to further expand its chip-on-wafer-on-substrate (CoWoS) capacity at a compound annual rate (CAGR) of over 60% until at least 2026, according to a report by AnandTech.

After leaving TSMC, Lin became the CEO of Skytech, where his extensive work experience helped him accumulate substantial expertise in packaging equipment manufacturing.

In 2022, Samsung established an Advanced Packaging Task Force, which was later transformed to its Advanced Packaging Business Team in 2023, of which Lin was said to join the team as Vice President, ijiwei notes.

However, industry insiders have revealed that the team was recently disbanded, and its members have returned to Samsung’s memory department and others, the report suggests. Additionally, Lin’s two-year contract with Samsung is said to be expire soon, and it seems unlikely that Samsung will renew it.

Being regarded as a “semiconductor packaging expert,” Lin’s next move is being closely watched. Certain Chinese semiconductor companies are rumored to get in contact with Lin, but it is expected that he will prioritize opportunities to collaborate with semiconductor companies in Taiwan, the report indicates.

The report notes that Samsung has confirmed that the team had been disbanded due to an internal organizational restructuring but declined to comment on personnel matters.

Earlier in May, as part of the restructuring process, the company has disbanded its Robot Business Team as well, which was responsible for developing its first wearable robot, “Bot Fit.”

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• [News] Samsung to Intensify Efforts for Capturing Intel’s Advanced Packaging Orders Shifting from TSMC
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(Photo credit: Samsung)

According to a report from Korean media outlet BusinessKorea, Rebellions’ CTO Oh Jin-wook announced that the company will adjust its production plans, bypassing the initially planned Rebel ‘Single’ product to focus on the mass production of the Rebel Quad AI chip by the end of the year.

This chip, manufactured using Samsung’s 4nm process, will be equipped with four Samsung’s 12-stack 5th generation High Bandwidth Memory (HBM3e), by the end of the year, offering a total memory capacity of 144GB.

Per the report, Oh explained that the company decided to accelerate the release of Rebel Quad due to internal assessments.

He also emphasized the superior power efficiency of Rebel, stating that it has demonstrated more than four times the power efficiency compared to products from Groq, a competing NPU company in the U.S.

Per a report from Reuters, Rebellions has recently signed a formal merger agreement with Sapeon Korea. The merged entity will retain the name Rebellions, and the combined company is expected to be valued at over 1 trillion Korean won, aiming to strengthen its competitiveness in the global AI chip market.

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• [News] South Korea’s AI Chip Startups Sapeon and Rebellions to Merge
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(Photo credit: Rebellions)

According to a report from the Commercial Times, SK hynix is expected to announce a plan of closer collaboration with TSMC and NVIDIA during the Semicon Taiwan exhibition in September, which is likely to focusing on the development of next-generation HBM. This partnership is expected to further strengthen their leadership in the supply of critical components for AI servers.

Semicon Taiwan will be held from September 4 to 6, and sources cited by the same report indicate that SK hynix President Justin Kim will attend the event and deliver a keynote speech for the first time.

Upon arriving in Taiwan, Justin Kim is expected to meet with TSMC executives. The report, citing rumors, suggests that NVIDIA CEO Jensen Huang might also join the meeting, further strengthening the alliance among the tech giants.

The core of this collaboration will revolve around HBM technology. In the past, SK hynix used its own processes to manufacture base dies up to HBM3e (the fifth-generation HBM).

However, industry sources cited by the report reveal that SK hynix will adopt TSMC’s logic process to manufacture the base die starting from HBM4, which would allow the memory giant to customize products for its clients in terms of performance and efficiency.

Industry sources cited by the report also indicate that SK hynix and TSMC have agreed to collaborate on the development and production of HBM4, scheduled for mass production in 2026.

This collaboration will reportedly involve manufacturing HBM4 interface chips using 12FFC+ (12nm class) and 5nm processes to achieve smaller interconnect spacing and enhance memory performance for AI and high-performance computing (HPC) processors.

Per SK hynix’s product roadmap, the company plans to launch a 12-layer stacked HBM4 in the second half of 2025 and 16-layer in 2026. TSMC, on the other hand, is also working to strengthen and expand its CoWoS-L and CoWoS-R packaging capacity to support the large-scale production of HBM4.

SK hynix has been the major supplier of HBM for NVIDIA’s AI GPUs, and with the upcoming Rubin series planned for 2026, it is expected to adopt HBM4 12Hi with 8 clusters per GPU. This partnership between SK hynix, TSMC and NVIDIA, therefore, is expected to expanding its influence and widening the gap with Samsung.

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• [News] SK hynix, TSMC, and NVIDIA Reportedly Forge Alliance to Develop Next-Generation HBM
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(Photo credit: SK hynix)

Earlier in June, Samsung updated its roadmap in the Angstrom era, stating that its 2nm node optimized with backside power delivery network (BSPDN), referred to as SF2Z, will enter mass production in 2027. Now, according to the latest report by the Korea Economic Daily, compared with the traditional front-end power delivery technology, BSPDN is said to reduce the size of Samsung’s 2nm chip by 17%.

Citing Lee Sungjae, vice president of the Foundry PDK Development Team at Samsung, on Thursday, the report also notes that by applying BSPDN to its 2nm chips, Samsung is expected to improve the product’s performance and power efficiency by 8% and 15%, respectively.

Lee’s remarks was the first time a Samsung foundry business executive provided details publicly regarding its BSPDN roadmap. The report explains that by positioning the power rails on the back of the wafer to remove bottlenecks between power and signal lines, the production of smaller chips would be easier.

However, Samsung is not the first semiconductor giant to adopt this technology. Among the Big Three in the foundry sector, Intel is at the forefront, aiming to produce chips with BSPDN technology, which it calls PowerVia, with Intel 20A (2 nm) in 2024. The tech giant also plans to implement PowerVia on Intel’s 20A along with the RibbonFET architecture for the full-surround gate transistor.

According to Intel, power lines typically occupy around 20% of the space on the chip surface, while its self-developed PowerVia’s backside power delivery technology saves this space, allowing more flexibility in the interconnect layers.

On the other hand, foundry leader TSMC reportedly plans to integrate its backside power delivery technology, Super PowerRail architecture, and nanosheet transistors in its A16 chip in 2026.

In addition to BSPDN, Samsung also revealed its roadmap about the next-generation gate-all-around (GAA) technology, which the company was first introduced in 2022, according to the report.

Samsung plans to begin mass production of 3 nm chips based on its second-generation GAA technology (SF3) in 2H24 and will also implement GAA in its upcoming 2 nm process, the report notes.

According to Lee, SF3 has enhanced chip performance by 30%, improved power efficiency by 50%, and reduced chip size by 35% compared to the chips produced with the first-generation GAA process. Coupling with the adoption of BSPDN, the two technologies can further reduce the chip size for Samsung.

Read more

• [News] Samsung Unveils Next-gen 2nm Node Roadmap; SF2Z with Backside Power Delivery to Enter Production in 2027
• [News] TSMC’s Backside Power Delivery Reportedly Set for 2026, Benefiting the Supply Chain

(Photo credit: Samsung)