Amid the wave of AI applications, the demand for high-performance memory continues to mushroom, with DRAM, represented by HBM, gaining significant traction. Meanwhile, to further meet market demand, memory manufacturers are  poised to embrace a new round of DRAM technological “revolution.”

• 4F Square DRAM being Developed Smoothly

According to a report from Korean media outlet Chosun Biz, Samsung Electronics Vice President Changsik Yoo recently announced that Samsung’s next-generation DRAM technology is progressing well. In addition to the successful mass production of 1b DRAM, the development of 4F Square DRAM technology is also proceeding smoothly, with the initial sample of 4F Square DRAM set to be developed by 2025.

Industry sources cited by WeChat account DRAMeXchange indicate that the early DRAM cell structure was 8F Square, while currently commercialized DRAM mainly uses 6F Square. Compared to these two technologies, 4F Square employs a vertical channel transistor (VCT) structure, which can reduce the chip surface area by 30%.

As the cell area decreases, DRAM density and performance increase. Therefore, driven by applications like AI, 4F Square technology is gradually sought after by major storage manufacturers.

Previously, Samsung stated that many companies are working to transition their technology to 4F Square VCT DRAM, although some challenges need to be overcome, including the development of new materials like oxide channel materials and ferroelectrics.

Industry sources believe that the initial sample of Samsung’s 4F Square DRAM in 2025 might be for internal release. Another semiconductor manufacturer, Tokyo Electron, estimates that DRAM using VCT and 4F Square technology will come out between 2027 and 2028.

Furthermore, earlier media reports mentioned that Samsung plans to apply Hybrid Bonding technology to support the production of 4F Square DRAM. Hybrid Bonding is a next-generation packaging technology referring to vertically stack chips to increase cell density and thus improve performance, which will also exert an influence on the development of HBM4 and 3D DRAM.

• HBM4 on the Horizon

In the era of AI, HBM, particularly HBM3e, has thrived in the memory market, prompting fierce competition among the three major DRAM manufacturers. A new race is now underway, primarily focusing on the next-generation HBM4 technology.

In April of this year, SK Hynix announced a partnership with TSMC to jointly develop HBM4. It is reported that the two companies will first work on performance improvements for the base die fitted at the bottom layer within the HBM package. To focus on the development of next-generation HBM4 technology, Samsung has established a new “HBM Development Team.”

In July, Choi Jang-seok, head of the New Business Planning Group in Samsung Electronics’ memory division, revealed that the company is developing a high-capacity HBM4 memory with a single stack of up to 48GB, expected to go into production next year. Recently, Samsung reportedly plans to use a 4nm advanced process to produce HBM4 logic die. Micron, on the other hand, plans to introduce HBM4 between 2025 and 2027 and transition to HBM4E by 2028.

Aside from manufacturing processes, DRAM manufacturers are actively exploring hybrid bonding technology for future HBM products. Compared to existing bonding processes, hybrid bonding eliminates the need for bumps between DRAM memory layers, instead directly connecting the upper and lower layers, copper to copper. This significantly improves signal transmission speed, better matching the high bandwidth requirements of AI computing.

In April of this year, Korean media outlet The Elec reported that Samsung successfully manufactured a 16-layer stacked HBM3 memory based on hybrid bonding technology, with the memory sample functioning normally. This 16-layer stacked hybrid bonding technology will be used to produce HBM4 at scale in the future. SK Hynix plans to adopt hybrid bonding in its HBM production by 2026. Micron is also developing HBM4 and is considering related technologies, including hybrid bonding, which are all under research at present.

• The Development of 3D DRAM Picks up Steam

3D DRAM (Three-dimensional dynamic random-access memory) represents a new DRAM technology with a novel memory cell structure. Unlike traditional DRAM, which places memory cells horizontally, 3D DRAM vertically stacks memory cells, greatly increasing storage capacity per unit area and improving efficiency. This makes it a key development for the next generation of DRAM.

In the memory market, 3D NAND Flash has already achieved commercial application, while 3D DRAM technology is still under research and development. However, as AI, big data, and other applications enjoy burgeoning growth, the demand for high-capacity, high-performance memory will surge, and 3D DRAM is expected to become a mainstream product in the memory market.

HBM technology has paved the way for the 3D evolution of DRAM, enabling DRAM to transition from traditional 2D to 3D. However, current HBM cannot be considered as true 3D DRAM technology. Samsung’s 4F Square VCT DRAM is closer to the concept of 3D DRAM, but it is not the only direction or goal for 3D DRAM. Memory manufacturers have more ideas and creativity in 3D DRAM.

Samsung plans to achieve the commercialization of 3D DRAM by 2030. In 2024, Samsung showcased two 3D DRAM technologies, including VCT and stacked DRAM. Samsung first introduced VCT technology, then upgraded to stacked DRAM by stacking multiple VCTs together to continuously improve DRAM capacity and performance.

Samsung states that stacked DRAM can fully utilize the Z-axis space, accommodating more memory cells in a smaller area, with a single chip capacity exceeding 100Gb. In May of this year, Samsung noted that it, along with other companies, successfully manufactured 16-layer 3D DRAM, but emphasized that it is not ready for mass production. 3D DRAM is expected to be produced using wafer-to-wafer hybrid bonding technology, and BSPDN (Backside Power Delivery Network) technology is also considered.

Regarding Micron, industry sources cited by DRAMeXchange reveal that Micron has filed for a 3D DRAM patent application different from Samsung’s, aiming to alter the shape of transistors and capacitors without placing cells.

BusinessKorea reported in June that SK Hynix achieved a manufacturing yield of 56.1% for its 5-layer stacked 3D DRAM. This means that out of around 1000 3D DRAMs produced on a single test wafer, about 561 viable devices were manufactured. The experimental 3D DRAM demonstrated characteristics similar to the currently used 2D DRAM, marking the first time SK Hynix disclosed specific numbers and features of its 3D DRAM development.

Besides, American company NEO Semiconductor is also engaging in the development of 3D DRAM. Last year, NEO Semiconductor announced the launch of the world’s first 3D DRAM prototype: 3D X-DRAM. This technology resembles 3D NAND Flash, namely increasing memory capacity by stacking layers, offering high yield, low cost, and remarkably high density.

NEO Semiconductor plans to launch the first generation of 3D X-DRAM in 2025, featuring a 230-layer stack and a core capacity of 128Gb, which is several times higher than the 16Gb capacity of 2D DRAM.

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• [News] Korean Semiconductor Exports Hit a New High, with Memory Shipment up by 88.7%
• [News] Korean Advanced Packaging Industry’s Rise Delayed by TSMC and ASE Expansion

(Photo credit: SK Hynix)

As the industry is entering the Angstrom era with semiconductor giants eagerly applying EUV machines to the advanced nodes, more details about Samsung’s 2nm have surfaced. According to the latest report by TheElec, Samsung’s 2nm process will feature 30% more extreme ultraviolet (EUV) layers than the 3nm node.

The report notes that Samsung’s 3nm node has 20 EUV mask layers, while the layers of the 2nm node will be increased to late-20. As the cost of manufacturing rises with the number of EUV mask layers, whether the wafer average selling price of Samsung’s 2nm will significantly increase attracts attention.

According to the report, the South Korean semiconductor giant first implemented EUV technology in its logic process nodes with 7nm in 2018. Since then, Samsung has increased the number of EUV layers or process steps with each subsequent node, moving from 5nm to 3nm. The report also states that Samsung’s 1.4nm process, set to begin production in 2027, is expected to feature over 30 EUV layers.

Meanwhile, Samsung is also using EUV in its DRAM production. For its Gen 6 10nm DRAM, Samsung has implemented up to 7 EUV layers, compared to 5 layers used by SK Hynix, TheElec states.

In comparison, according to an earlier report by AnandTech, TSMC’s standard N3 node includes up to 25 EUV layers. TSMC employs EUV double-patterning on some of these layers to achieve greater logic and SRAM transistor density compared to its N5 node.

It is also worth noting that as EUV layers increase with each node, foundries are vying to secure more EUV machines from ASML. The Dutch lithography equipment giant is said to ship over 70 EUV machines to TSMC in 2024 and 2025 in response to the strong demand of 2nm and 3nm, according to a report by MoneyDJ.

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• [News] Samsung Officially Secures Its First 2nm Order, Making AI Chips for Preferred Networks
• [News] Intel Secures First Batch of High-NA EUV Equipment from ASML, Ahead of Samsung and SK Hynix

(Photo credit: ASML)

Earlier on July 10^th, in the Galaxy Unpack 2024 event in Paris, Samsung introduced its AI smartphone Galaxy Z Fold6 and Galaxy Z Flip6, along with the “Google Gemini” app installed in the models. However, according to the reports by Reuters and Business Korea, these two tech giants may be facing the investigation of the European Union (EU) antitrust regulators, on whether the collaboration might impede market access for other AI developers or limit competition.

It has been a while since the two tech heavyweight started to team up on AI. Samsung’s first AI phone, Galaxy S24, released earlier this year, has featured its self-developed AI, Gauss, as well as Google’s Gemini Nano.

The EU has ramped up its market monitoring efforts following the implementation of the Digital Markets Act (DMA) in March, focusing on major global tech companies. The DMA identifies seven companies—Google, Amazon, Apple, Meta, Microsoft, Booking and ByteDance —as ‘gatekeepers’ and imposes specific regulations on them to ensure fair competition in the digital market, Business Korea noted.

Now the spotlight has been shifted to the AI sector. According to Reuters, EU antitrust regulators are inquiring whether Google’s multi-year generative AI deal with Samsung hampers rival chatbots on Samsung smartphones. The report noted that last month, the European Commission announced it would send requests for information to understand the impact of the deal, which involves Samsung embedding Google’s Gemini Nano in its Galaxy S24 series smartphones.

According to the Reuters report, regulators are investigating if the pre-installation of Gemini Nano limits the functionality of other chatbots and applications on Samsung smartphones. The EU also asked companies whether they had attempted to enter into pre-installation agreements with Samsung for their chatbots and, if so, requested explanations for any failures. Respondents are required to complete the urvey by this week.

If anti-competitive practices are confirmed, an antitrust investigation against Google and Samsung could be initiated, Reuters stated.

According to Business Korea, after the Galaxy Unpacked 2024 event, TM Roh, President of Samsung Electronics (Head of MX Business Division), addressed regulatory risks during a press conference, saying the company is having various discussions internally and externally regarding EU regulations.

Roh also emphasized Samsung’s commitment to data security, stating that sensitive information is processed on-device (without connecting to external servers), making it inaccessible even to the company,” and highlighted the company’s approach to giving consumers the choice of using AI functions on-device or via the cloud.

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• [News] NVIDIA Faces Potential Antitrust Charges in France, U.S. and EU Close Behind
• [News] Samsung Rumored to Mass-Produce HBM4 with 4nm Process

(Photo credit: Samsung)

As Samsung eagerly accelerates its pace on the HBM3e certification with NVIDIA, SK hynix, the current HBM market leader, is reportedly planning another move to strengthen its relationship with the AI giant. According to a report by Korean media Money Today, SK hynix is teaming up with Amkor Technology to target the silicon interposer market, eyeing to become a supplier for NVIDIA.

Citing sources from the semiconductor industry, the report notes that SK hynix has discussed with Amkor, the world’s second-largest OSAT (Outsourced Semiconductor Assembly and Test) company, about sending interposer samples. The process involves SK hynix sending its HBM and interposers to Amkor, which then combines them with GPUs from customers like NVIDIA to assemble AI accelerators.

A silicon interposer is a substrate on which GPUs and HBM are arranged and connected with the 2.5D/3D packaging. According to the report, drawing circuits on silicon to connect chips allows for more precise circuitry compared to using PCBs (Printed Circuit Boards) in traditional 2D packaging, which makes silicon interposers essential for packaging AI accelerators like NVIDIA’s A100 and H100.

Regarding the rumor, citing a SK hynix representative, the report states that the discussion is still in the early stages, while the company is conducting various reviews to provide interposers that meet customer demands.

It is worth noting that the entry barrier for silicon interposers seems to be high, as only a few semiconductor giants, including TSMC, UMC and Samsung, can supply silicon interposers with their own packaging technologies, such as TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) technology and Samsung’s I-Cube.

As Samsung is currently providing NVIDIA with its silicon interposers and I-Cube packaging services, SK hynix tries to further expand its leadership in HBM by entering the silicon interposer sector, the report notes, which may also alleviate the supply shortage for HBM and interposers as NVIDIA’s AI accelerators are in high demand.

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• [News] SK hynix, TSMC, and NVIDIA Reportedly Forge Alliance to Develop Next-Generation HBM
• [News] Samsung, SK Hynix and Micron Ramp Up HBM Production, Reportedly Doubling Output Next Year

(Photo credit: SK hynix)

According to TrendForce’s latest memory spot price trend report, DRAM spot prices have finally stabilized as Samsung is committed to propping them up. Spot prices of DDR4 products, in particular, continue the momentum. As for NAND flash, demand for a small extent of inventory replenishment remains possible for 3Q24, which may help the sales performance from the spot market to improve from that of 2Q24. Details are as follows:

DRAM Spot Price:

DRAM spot prices, which had experienced a long period of decline, have finally stabilized as Samsung is committed to propping them up. Spot prices of DDR4 products, in particular, have risen slightly. Additionally, since spot prices are currently lower than contract prices for both DDR4 and DDR5 products, module houses and other buyers prefer spot trading. This, in turn, has helped stabilize spot prices. The average spot price of mainstream chips (i.e., DDR4 1Gx8 2666MT/s) has increased by 0.81% from US$1.979 last week to US$1.995 this week.

NAND Flash Spot Price:

Spot prices have started to stabilize recently as a result of reluctance in truncation from spot traders and module houses, as well as the consideration on how the growth of demand has been exceedingly confined by the drop of prices. Demand for a small extent of inventory replenishment remains possible for 3Q24, when sales performance from the spot market is expected to improve from that of 2Q24. On the whole, spot prices would first maintain equilibrium whilst awaiting for the final development of suppliers’ contract prices and the market status for 3Q24, before deciding on subsequent actions. Spot prices of 512Gb TLC wafers have dropped by 0.58% this week, arriving at US$3.272.