According to a report from Korean media outlet Korea Economic Daily (KED), South Korean tech giant Samsung Electronics is looking to borrow up to KRW 5 trillion (approximately USD 3.6 billion) from the state-run Korea Development Bank (KDB) to finance its expansion of chip production facilities both in Korea and abroad.

According to sources cited in the same report, Samsung is in the final stages of negotiations with the KDB regarding the exact amount of the loan and the interest rates. Additionally, the report mentioned that Samsung’s competitor, SK Hynix, is also considering borrowing up to KRW 3 trillion from the KDB for its chip investments.

Regarding this, the bank is reportedly prepared to extend up to KRW 5 trillion to Samsung at an interest rate of about 3.5% per year. If finalized, this would be the first time in two decades that Samsung has borrowed such a large sum.

Notably, according to a previous report from the Chosun Daily, starting from July, the South Korean government will begin offering incentives and subsidies to semiconductor companies, launching a 26 trillion won (USD 19 billion) funding program to support the industry.

Initially, South Korea will start with an 18 trillion won (USD 12.94 billion) investment program, including preferential loans and investment funds. According to a statement from the Ministry of Economy and Finance, eligible companies will be able to borrow from a 17 trillion won low-interest loan program.

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(Photo credit: Samsung)

According to a report from South Korean media Maeil Business Newspaper, Samsung Electronics plans to raise prices for server DRAM and enterprise NAND flash by 15% to 20% in the third quarter due to surging demand for artificial intelligence (AI). This move is expected to improve the company’s performance in the second half of the year, while boosting momentum for some Taiwanese companies like Nanya Technology, ADATA, TeamGroup and Transcend in the coming quarters.

Industry sources cited by a report from Economic Daily News believe that with manufacturers defending prices, there is strong support for the market. Additionally, as the three major manufacturers focus on developing high-bandwidth memory (HBM), which limits the output of DDR4 and DDR3, it helps maintain a healthy state for the DRAM industry.

Per Maeil Business Newspaper, sources have revealed on June 26th that Samsung Electronics has recently notified major customers about the planned price increase. The Device Solutions (DS) division, responsible for Samsung’s semiconductor business, held a global strategy meeting at its Hwaseong plant in Gyeonggi-do on the same day, where this matter was discussed.

The report further stated that Samsung Electronics had already increased the prices of NAND flash supplied to enterprises by at least 20% in the second quarter, anticipating that the AI boom will drive higher server demand in the second half of the year.

According to data from DRAMeXchange, the global sales of enterprise NAND flash reached $3.758 billion in the first quarter of this year, marking a 62.9% increase from the previous quarter. With the rising demand, some products are experiencing shortages.

TrendForce also notes that with a slight improvement in server demand, Samsung has indicated it will adopt a more aggressive pricing strategy for server DRAM and enterprise SSDs for 3Q24 deals. TrendForce’s price projections posit that server DRAM prices are expected to increase by more than 10% QoQ, with enterprise SSDs enjoying a similar price range. However, due to sluggish smartphone demand, price increases in mobile categories are expected to be more modest.

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• [Insights] Memory Spot Price Update: DRAM Remains Weak Despite Samsung’s Capacity Shift to HBM
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(Photo credit: Samsung)

Rumors have been circulating regarding Samsung’s 3nm yield recently. The latest market speculation on June 25^th alleged that Samsung’s foundry plant encountered a defect impacting 2,500 lots in the 3nm second-generation process, reportedly leading to a loss of 1 trillion won (USD 720 million), according to the latest report by the Chosun Daily.

On June 26^th, the semiconductor giant denied the rumors of a major defect in the production of semiconductor wafers at its foundry division in South Korea. Market speculations emerged earlier, suggesting that all the affected wafers, which equal to 2,500 lots, had to be discarded, the report noted. The volume corresponds to roughly 65,000 12-inch equivalent wafers per month.

According to the Chosun Daily, Samsung claimed that the rumor of “discarding them (the affected wafers) all” circulating in the stock market are unfounded. The current status of the products from the affected production line is still under evaluation, the report said.

Citing industry insiders familiar with the matter, the Chosun Daily noted that the reported figures might be exaggerated, pointing out that Samsung’s 3nm production capacity is less than 60,000 wafers per month. Furthermore, there are numerous inspection processes in place throughout the production line, indicating that such a large-scale defect may be improbable.

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• [News] Samsung’s 3nm Yield Reportedly Below 20%, Struggling for Mass Production

(Photo credit: Samsung)

After ending production cuts amidst a recovery in the memory industry, Kioxia disclosed its plans on the 3D NAND roadmap last week. According to reports from PC Watch and Blocks & Files, Kioxia stated that achieving a 1,000-layer level by 2027 would be possible.

According to the reports, the number of 3D NAND layers has generally increased from 24 in 2014 to 238 in 2022, representing a tenfold rise over eight years. Kioxia stated that achieving a 1,000-layer level by 2027 would be possible at a rate of increase of 1.33 times per year.

The Japanese memory chipmaker seems to be more ambitious than Samsung regarding the battle of layers. In May, Samsung revealed its target to release advanced NAND chips with over 1000 layers by 2030. According to Wccftech, the South Korean memory giant plans to apply new ferroelectric materials on the manufacturing of NAND to achieve this goal.

According to the latest analysis from TrendForce, Kioxia has benefited from the recovery of the memory industry, recently receiving subsidies from the Japanese government and additional financing from a consortium of banks. Furthermore, the company plans to launch an IPO by the end of the year. These measures have provided Kioxia with ample financial resources to pursue technological advancements and cost optimization.

TrendForce further notes that Kioxia has ambitious plans to achieve 1000-layer technology by 2027, which is the highest number of layers announced by any manufacturer so far. However, to reach the milestone, it will be necessary to transition from TLC (3 bits per cell) to QLC (4 bits per cell), and possibly even to PLC (5 bits per cell). The technical challenges involved are significant, and whether Kioxia can achieve this market milestone by 2027 remains to be seen.

The Battle of Layers between Memory Giants

Kioxia and its partner Western Digital showcased their 218-layer technology in 2023 following the 162-layer milestone. Its current announcement to achieve the 1000-layer technology by 2027 would be a huge leap from that.

The battle of layers between memory giants has been intensifying as other memory heavyweights had already surpassed the 200-layer milestone. Earlier in April, Samsung confirmed that it has begun mass production for its one-terabit (Tb) triple-level cell (TLC) 9th-generation vertical NAND (V-NAND), with the number of layers reaching 290, according an earlier report by The Korea Economic Daily. For now, the company aims to stack V-NAND to over 1000 layers by 2030.

SK Hynix unveiled the world’s highest-layer 321-layer NAND flash memory samples in August 2023, claiming to have become the industry’s first company developing NAND flash memory with over 300 layers, with plans for mass production by 2025. Micron has also started to mass produce its 232-layer QLC NANDs in 2024.

Uncertainties behind Kioxia’s Optimism

However, to Kioxia, there are more challenges to overcome, as technological obstacles and Western Digital’s stance add uncertainties to its ambition. According to the report from Blocks & Files, increasing density in a 3D NAND die involves more than just adding layers, as each layer’s edge must be exposed for memory cell electrical connectivity. This results in a staircase-like profile, and as the number of layers grows, the die area needed for the staircase expands as well.

Therefore, to increase density, it is necessary to shrink the cell size both vertically and laterally, and to raise the bit level as well. All these scaling factors, including layer counts, vertical cell size reduction, lateral cell size reduction, and cell bit level increases, present their own technological challenges.

Moreover, according to Blocks & Files, WD has concerns regarding the manufacturing capital costs and the return on investment from selling chips and SSDs made with the fabricated NAND dies.

Citing Western Digital EVP Robert Soderbery in June, the report noted that in the 3D era, NAND manufacturing requires higher capital intensity but offers a lower cost reduction as bit density increases. The company even described the situation as the “end of the layers race,” indicating that there would be a slowdown in the rate of NAND layer count increases to optimize capital deployment.

How long would the battle of layers continue, and how far would it go? Technological breakthroughs as well as the willingness to endure higher capital intensity while the cost reduction being relatively limited may be key.

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(Photo credit: Kioxia)

According to TrendForce’s latest memory spot price trend report, the spot price of DRAM remains weak, as Samsung’s reallocation of its D1A process to the manufacturing of HBM products did little help. As for NAND flash, overall transactions are also sitting on the enervated end due to weakening market demand. Details are as follows:

DRAM Spot Price:

A fire-related incident occurred at Micron’s fab in Taichung on June 20th, but no actual losses (in bit terms) have been reported. In response to this event, module houses did temporarily suspend quoting, but they soon resumed trading activities. Overall, the event has had no positive effect on the spot price trend, which remains relatively weak. Similar to last week, spot trading has been fairly tepid, and prices of DDR4 products have fallen more significantly compared to DDR5 products. With Samsung reallocating its D1A process to the manufacturing of HBM products, spot prices of DDR5 products have actually experienced sporadic hikes for a while. Mainstream die DDR4 1Gx8 2666 MT/s saw a price increase of 1.36% this week (US$1.835 to US$1.860).

NAND Flash Spot Price:

Module houses have started adopting even more aggressive pricing strategies to effectively control their inventory, though overall transactions are sitting on the enervated end due to weakening market demand. TrendForce believes that inventory pressure would continue to bring down spot prices, which dropped to US$3.302 for 512Gb TLC wafers this week at a 0.21% reduction.