Recently, it was reported that to meet the increasing demand for memory chips driven by the artificial intelligence (AI) boom, both Samsung Electronics and Micron set about ramping up their memory chip production capacity. Samsung plans to restart construction of the new Pyeongtaek plant (P5) infrastructure as early as 3Q24. Micron is building HBM testing and mass production lines at its headquarters in Boise, Idaho, U.S. and is considering producing HBM in Malaysia for the first time to meet the growing demand brought by the AI surge.

Samsung Restarts the Construction of P5 Plant

As per foreign media reports, Samsung has decided to restart the construction of the P5 infrastructure, which is expected to resume as early as 3Q24 and be completed in April 2027, though the actual date of starting production could be earlier.

Previously, P5 reportedly suspended construction at the end of January, which was said to be a temporary measure to coordinate progress, with investment not yet been finalized, as stated by Samsung at that time. Industry analysts interpret Samsung’s decision to resume P5 construction as a response to the AI-driven surge in demand for memory chip.

It is reported that the Samsung P5 plant is a large wafer fab with eight cleanrooms, while P1 to P4 only have four respectively, which makes Samsung’s plan to achieve large-scale production to meet market demand possible. However, no official announcement regarding the specific use of P5 has been disclosed so far.

According to Korean media reports, industry sources stated that Samsung held an internal management committee conference of the board of directors on May 30, during which they submitted and passed the agenda for the P5 infrastructure construction. The management committee was chaired by CEO and head of the DX division, Jong-hee Han, involving other members such as MX business head Noh Tae-moon, management support director Park Hak-gyu, and head of the memory business division Lee Jeong-bae.

Hwang Sang-joong, vice president and head of DRAM Product and Technology at Samsung, stated in March this year that HBM output for this year was expected to be 2.9 times that of last year. The company also announced its HBM roadmap, projecting that HBM shipment in 2026 would be 13.8 times the 2023 output, and by 2028, the annual HBM output would further increase to 23.1 times the 2023 level.

Micron Builds HBM Testing and Mass-Production Lines in the U.S.

On June 19, multiple media reported that Micron is building HBM testing and mass production lines at its headquarters in Boise, Idaho, and is considering producing HBM in Malaysia for the first time to meet the increased demand driven by the AI boom. Micron’s Boise wafer fab is reportedly to put into operation in 2025 and start DRAM production in 2026.

Previously, Micron announced plans to increase its HBM market share from the current “mid-single digits” to around 20% within a year. As of now, Micron has been expanding its memory capacity in various locations.

At the end of April, Micron officially announced that it had received USD 6.1 billion of government subsidies from the U.S. CHIPS and Science Act. These funds, along with additional state and local incentives, will support Micron in building a leading DRAM memory manufacturing plant in Idaho and two advanced DRAM memory manufacturing plants in Clay, New York.

The Idaho plant commenced construction in October 2023. Micron revealed that the plant is expected to run in 2025 and start DRAM production in 2026, with DRAM output increasing in line with industry demand. The New York project is in the phase of initial design, field study, and license application (NEPA application included). Construction of the wafer fab is expected to begin in 2025 and production in 2028, which will increase depending on market demand over the next decade. The press release noted that the U.S. government’s subsidies will support Micron’s plan to invest around USD 50 billion of total capital expenditures to lead domestic memory manufacturing by 2030.

In May, Japanese media Nikkan Kogyo Shimbun reported that Micron will pour JPY 600 to 800 billion to build an advanced DRAM chip plant using EUV lithography in Hiroshima, Japan. Construction is expected to start in early 2026 and be completed in late 2027 at the earliest. Japan had previously approved up to JPY 192 billion of subsidies to support Micron’s plant construction and next-generation chip production in Hiroshima.

The new Micron plant in Hiroshima will be located near the existing Fab 15, focusing on DRAM production, excluding back-end packaging and testing, with priority given to the fabrication of HBM products.

In October 2023, Micron inaugurated its second smart (Advanced assembly and test) plant in Penang, Malaysia, with an initial investment of USD 1 billion. Following the completion of the first plant, Micron allocated an additional USD 1 billion to expand the second smart plant, expanding its building area to 1.5 million square feet.

(Photo credit: Samsung)

TSMC is said to be entering the fan-out panel-level packaging (FO-PLP) sector, according to a previous report from Nikkei. Now, a report from Business Korea noted that Samsung is making significant strides in the PLP field, as the tech giant acquired the PLP business from Samsung Electro-Mechanics as early as in 2019.

It is interesting to note that TSMC has returned to the development of PLP now, while this technology is actually regarded by Samsung as the “secret weapon” to challenge TSMC’s InFO-WLP technology a few years ago.

In 2015, TSMC has secured all of Apple’s A10 orders by offering the InFO-WLP (Integrated Fan-Out Wafer Level Packaging) technology. According to a previous report by Korea media outlet ETNews, Samsung was prompted to take action, making the company to cooperate with Samsung Electro-Mechanics to start developing FO-PLP technology.

In 2019, Samsung acquired the PLP business from Samsung Electro-Mechanics for 785 billion won (approximately USD 581 million), a strategic move that has paved the way for its current advancements, according to Business Korea.

At the shareholders’ meeting in March this year, Kyung Kye-hyun, the former head of Samsung Electronics’ semiconductor (DS) division, highlighted the importance of PLP technology to the industry, Business Korea noted. Kyung stated that AI semiconductor dies, which are typically 600mm x 600mm or 800mm x 800mm in size, require technologies like PLP, while Samsung is actively developing this technology and collaborating with clients.

Samsung currently offers advanced packaging services such as I-Cube 2.5D packaging, X-Cube 3D IC packaging, and 2D FOPKG packaging. For applications requiring low-power memory integration, such as mobile phones or wearable devices, Samsung already provides platforms like fan-out panel-level packaging and fan-out wafer-level packaging.

On the other hand, TSMC is reportedly collaborating with equipment and material suppliers to develop the panel-level packaging technology, though the research is still in its early stages. By using a rectangular substrate for packaging, replacing the current traditional circular wafer, more chipsets can be accommodated on a single wafer.

The report by Nikkei mentioned that TSMC is currently experimenting with rectangular substrates measuring 515 mm in length and 510 mm in width, providing more than three times the usable area of a 12-inch wafer.

For now, TSMC’s CoWoS advanced chip packaging can combine two sets of NVIDIA Blackwell GPU chips and eight sets of high-bandwidth memory (HBM). As single chips need to accommodate more transistors and integrate more memory, the mainstream 12-inch wafer might not be sufficient for packaging advanced chips soon. The reason behind TSMC’s foray into PLP research, therefore, may be interpreted as a response to the booming AI demand.

Read more

• [News] TSMC Reportedly Develops Panel-Level Packaging, Another New Chip Packaging Tech
• [News] New Battleground for TSMC, Samsung & Intel in Panel-Level Packaging

(Photo credit: Samsung)

According to a report by Korean media outlet Business Korea, SK Hynix recently shared its latest breakthrough on its 3D DRAM at VLSI 2024 last week, announcing that the manufacturing yield of its 5-layer stacked 3D DRAM has reached 56.1%.

This means that out of roughly 1,000 3D DRAM units manufactured on a single test wafer, about 561 functional devices were successfully manufactured, the report further explains. The experimental 3D DRAM exhibits characteristics similar to the currently used 2D DRAM, marking the first time SK Hynix has disclosed specific numbers and characteristics of its 3D DRAM development.

However, SK Hynix also noted that while 3D DRAM holds great potential, a significant amount of development is still required before it can be commercialized. The memory giant also reportedly pointed out that unlike the stable operation of 2D DRAM, 3D DRAM exhibits unstable performance characteristics, and stacking 32 to 192 layers of memory cells is necessary for widespread use.

3D DRAM is also a key development area for other major memory manufacturers like Samsung Electronics and Micron. Samsung Electronics has successfully stacked 3D DRAM up to 16 layers and plans to mass-produce 3D DRAM around 2030. Micron currently holds 30 patents related to 3D DRAM, and if there are breakthroughs in 3D DRAM technology, it could produce better DRAM products than existing ones without the need for EUV equipment.

The DRAM market remains highly concentrated, currently dominated by key players such as Samsung Electronics, SK Hynix, and Micron Technology, collectively holding over 96% of the entire market share.

Read more

• [News] Samsung and SK hynix to Implement Hybrid Bonding with 3D DRAM
• [News] The Quiet Beginning of the 3D DRAM Market Share Battle

(Photo credit: SK Hynix)

According to a report from Korean media outlet ZDNet Korea, the yield rate for Samsung Electronics’ latest Exynos 2500 processor has improved to slightly below 20% from single digits in the first quarter. However, the current yield rate is still said to be falling short of mass production standards. It remains uncertain whether it can be used in the flagship Galaxy S25 series smartphones in the future.

The report further indicates that this yield rate is still insufficient for mass production, which typically requires yields to be increased to over 60%. Therefore, Samsung Electronics’ System LSI department reportedly plans to work on improving the yield rate of the Exynos 2500 processor in the second half of this year.

The report states that it is still uncertain whether the Exynos 2500 processor can be used in the future Galaxy S25 series flagship smartphones. Since there is still considerable time before the official launch of the Galaxy S25 series, Samsung hopes to improve the yield rate of the Exynos 2500 processor to 60% by October this year.

On the other hand, TSMC is overwhelmed with 3nm orders, with major companies like Apple, NVIDIA, AMD, Qualcomm, Intel, and MediaTek all utilizing TSMC’s 3nm process. Per a report from TechNews, during TSMC’s technology forum on May 23, the 3nm production capacity this year has more than tripled compared to last year, but this is actually still not enough, so efforts are still being made to meet customer demand.

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• [News] Major Clients Reportedly Fully Allocate TSMC’s Production Capacity Until 2026, 3nm Process in High Demand
• [News] Samsung Reportedly to Challenge Apple/TSMC with 3nm Exynos W1000

(Photo credit: Samsung)

According to a previous report from Nikkei citing sources, TSMC is rumored to be entering the fan-out panel-level packaging sector. As cited in a report from UDN, Intel and Samsung have also announced plans to invest in this area. With TSMC, the leading wafer foundry, joining the fray, the three semiconductor giants are set to compete in fan-out panel-level packaging.

TSMC stated yesterday that the company is closely monitoring the progress and development of advanced packaging technologies, including panel-level packaging technology.

Nikkei reported that in response to future AI demand trends, TSMC is collaborating with equipment and material suppliers to develop new advanced chip packaging technology. This technology uses a rectangular substrate for packaging, replacing the current traditional circular wafer, to accommodate more chipsets on a single wafer. The report further mentioned that TSMC’s research is still in its early stages and might take several years to commercialize, but it represents a significant technological shift.

Reportedly, TSMC previously considered the challenge of using rectangular substrates to be too high, requiring substantial time and effort from both the company and its suppliers, along with upgrades or replacements of many production tools and materials.

Nikkei  also mentioned that TSMC is currently experimenting with rectangular substrates measuring 515 mm in length and 510 mm in width, providing more than three times the usable area of a 12-inch wafer.

TSMC is expanding its advanced chip packaging capacity, with the expansion of the Taichung plant mainly for NVIDIA, while the Tainan plant is primarily for Amazon and its chip design partner Alchip Technologies.

TSMC’s CoWoS advanced chip packaging can combine two sets of NVIDIA Blackwell GPU chips and eight sets of high-bandwidth memory (HBM). As single chips need to accommodate more transistors and integrate more memory, the mainstream 12-inch wafer might not be sufficient for packaging advanced chips in two years.

Samsung and Intel have also recognized the aforementioned issues and are investing in next-generation advanced packaging technologies.

Samsung currently offers advanced packaging services such as I-Cube 2.5D packaging, X-Cube 3D IC packaging, and 2D FOPKG packaging. For applications requiring low-power memory integration, such as mobile phones or wearable devices, Samsung already provides platforms like fan-out panel-level packaging and fan-out wafer-level packaging.

Intel is planning to launch the industry’s first glass substrate solution for next-generation advanced packaging, with mass production scheduled between 2026 and 2030. Intel anticipates that data centers, AI, and graphics processing—markets that require larger volume packaging and higher-speed applications and workloads—will be the first to adopt this technology.

Read more

• [News] TSMC Reportedly Develops Panel-Level Packaging, Another New Chip Packaging Tech
• [News] Samsung Reportedly Targets Q4 Trial Production of SiP Glass Substrate, Competing with Intel in the Advanced Packaging Market

(Photo credit: Intel)