According to the latest report by TheElec, though Samsung has been using thermal compression (TC) bonding until its 12-stack HBM, the company now confirms its belief that hybrid bonding is necessary for manufacturing 16-stack HBM.

Regarding its future HBM roadmap, Samsung reportedly plans to produce its HBM4 sample in 2025, which will mostly be 16 stacks, with mass production slated for 2026, the report noted. According to TheElec, earlier in April, Samsung used hybrid bonding equipment from its subsidiary, Semes, to produce a 16-stack HBM sample, of which it indicated to operate normally.

Citing information Samsung revealed during the 2024 IEEE 74th Electronic Components and Technology Conference last month, TheElec learned that Samsung considered hybrid bonding essential for HBM with 16 stacks and above.

According to the report, Samsung has been using thermal compression (TC) bonding until its 12-stack HBM. However, now it emphasized on hybrid bonding’s ability to reduce height, which would be indispensable for 16-stack HBM. By further narrowing the gap between chips, 17 chips (one base die and 16 core dies) can be fitted within a 775-micrometer form factor.

According to an earlier report from TechNews, Samsung and Micron use TC-NCF technology (thermal compression with non-conductive film) on HBM production, which requires high temperatures and high pressure to solidify materials before melting them, followed by cleaning. The industry has relied on traditional copper micro bumps as the interconnect scheme for packages, while their sizes pose challenges when trying to allow more chips to be stacked at a lower height.

Samsung stated that though making the core die as thin as possible or reducing the bump pitch could help, these methods have reached their limits. Sources cited by the Elec mentioned that it is very challenging to make the core die thinner than 30 micrometers. Also, using bumps to connect the chips has limitations due to the volume of the bumps. Thus, hybrid bonding technology may emerge as a promising solution.

While the current technology uses micro bump materials to connect DRAM modules, hybrid bonding, which could stack chips veritically by using through-silicon-via (TSV), can eliminate the need for micro bumps, significantly reducing chip thickness.

On the other hand, according to another report by Business Korea, SK hynix has shown its confidence in the HBM produced with Mass Reflow-Molded Underfill (MR-MUF) technology. MR-MUF technology attaches semiconductor chips to circuits, using EMC (liquid epoxy molding compound) to fill gaps between chips or between chips and bumps during stacking.

SK hynix reportedly plans to begin mass production of 16-layer HBM4 memory in 2026, and the memory heavyweight is currently researching hybrid bonding and MR-MUF for HBM4, but yield rates are not yet high, the report said.

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• [News] The HBM4 Battle Begins! Memory Stacking Challenges Remain, Hybrid Bonding as the Key Breakthrough
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(Photo credit: Samsung)

According to a report from TechNews, South Korean memory giant SK Hynix is participating in COMPUTEX 2024 for the first time, showcasing the latest HBM3e memory and MR-MUF technology (Mass Re-flow Molded Underfill), and revealing that hybrid bonding will play a crucial role in chip stacking.

MR-MUF technology attaches semiconductor chips to circuits, using EMC (liquid epoxy molding compound) to fill gaps between chips or between chips and bumps during stacking. Currently, MR-MUF technology enables tighter chip stacking, improving heat dissipation performance by 10%, energy efficiency by 10%, achieving a product capacity of 36GB, and allowing for the stacking of up to 12 layers.

In contrast, competitors like Samsung and Micron use TC-NCF technology (thermal compression with non-conductive film), which requires high temperatures and high pressure to solidify materials before melting them, followed by cleaning. This process involves more than 2-3 steps, whereas MR-MUF completes the process in one step without needing cleaning. As per SK Hynix, compared to NCF, MR-MUF has approximately twice the thermal conductivity, significantly impacting process speed and yield.

As the number of stacking layers increases, the HBM package thickness is limited to 775 micrometers (μm). Therefore, memory manufacturers must consider how to stack more layers within a certain height, which poses a significant challenge to current packaging technology. Hybrid bonding is likely to become one of the solutions.

The current technology uses micro bump materials to connect DRAM modules, but hybrid bonding can eliminate the need for micro bumps, significantly reducing chip thickness.

SK Hynix has revealed that in future chip stacking, bumps will be eliminated and special materials will be used to fill and connect the chips. This material, similar to a liquid or glue, will provide both heat dissipation and chip protection, resulting in a thinner overall chip stack.

SK Hynix plans to begin mass production of 16-layer HBM4 memory in 2026, using hybrid bonding to stack more DRAM layers. Kim Gwi-wook, head of SK Hynix’s advanced HBM technology team, noted that they are currently researching hybrid bonding and MR-MUF for HBM4, but yield rates are not yet high. If customers require products with more than 20 layers, due to thickness limitations, new processes might be necessary. However, at COMPUTEX, SK Hynix expressed optimism that hybrid bonding technology could potentially allow stacking of more than 20 layers without exceeding 775 micrometers.

Per a report from Korean media Maeil Business Newspaper, HBM4E is expected to be a 16-20 layer product, potentially debuting in 2028. SK Hynix plans to apply 10nm-class 1c DRAM in HBM4E for the first time, significantly increasing memory capacity.

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• [News] Reasons for Samsung’s HBM Chips Failing Nvidia Tests Revealed, Reportedly Due to Heat and Power Consumption Issues
• [News] HBM Boom May Lead to DRAM Shortages in the Second Half of the Year

(Photo credit: SK Hynix)

Samsung has been strengthening its alliance regarding the semiconductor packaging technology, attempting to narrow the technological gap with TSMC, according to the latest report by Business Korea.

Citing industry sources, Business Korea noted that Samsung is expected to expand its 2.5D and 3D MDI (Multi Die Integration) Alliance to include 30 partners this year, an increase of 10 within just one year.

The MDI Alliance, launched by Samsung Electronics in June, 2023, was established to address the rapid growth in the chiplet market for mobile and HPC applications, in which Samsung will collaborate with its partner companies as well as major players in memory, substrate packaging and testing.

According to Samsung’s press release, the MDI Alliance leads innovation in stacking technology by forming a packaging technology ecosystem for 2.5D and 3D Heterogeneous Integration. Together with partners across the ecosystem, Samsung will provide a one-stop turnkey service to better support customers’ technological innovation.

As demands from AI and data centers have been heated up, stacking and combining different chips are viewed as more cost-effective and efficient than further reducing the circuit size within a chip, which makes 2.5D and 3D IC packaging technology coveted by tech giants like NVIDIA and AMD.

Business Korea further stated that while Samsung does benefit from offering a ‘one-stop’ solution that integrates foundry, HBM, and packaging, successful collaboration is crucial to address the various software challenges that arise from chip integration. That is to say, to overcome this challenge, Samsung has formed a coalition with design firms, post-processing companies, and EDA (Electronic Design Automation) tool providers.

On the other hand, TSMC, the current market leader in 2.5D IC and 3D IC packaging, announced the new 3Dblox 2.0 open standard and its major achievements of its Open Innovation Platform (OIP) 3DFabric Alliance in September, 2023, while AMD confirmed its collaboration with TSMC on 3D IC packaging for the GPU giant’s MI300 AI accelerators, according to a press release by TSMC.

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• [News] Differences Between 3D-SIP and 3D-SIC: Why Are TSMC, Intel, and Samsung All Actively Involved?

(Photo credit: Samsung)

Qualcomm President & CEO Cristiano Amon, at COMPUTEX 2024, showcased devices powered by Snapdragon X Elite and Snapdragon X Plus processors, claiming them to be the only PCs capable of delivering Copilot+ PC experiences. Afterwards, during a media briefing, he disclosed Qualcomm’s plans on a dual-sourcing production strategy, indicating that the cooperation with Samsung has been considered, Korean media outlet Business Korea reported.

According to a previous report by Wccftech, Qualcomm’s Snapdragon 8 Gen 4, targeting to be launched in October, is rumored to utilize TSMC’s N3E node. However, the possibility of diversifying the production sources for Qualcomm’s “Snapdragon 8 Gen 5” smartphone chip has recently become a hot topic.

Regarding Qualcomm’s potential dual-sourcing policy, Amon emphasized that the primary focus should be on TSMC’s foundry production. However, he expressed willingness to collaborate with both TSMC and Samsung Electronics, according to Business Korea.

Initially, Samsung’s foundry was tasked with producing the first-generation Snapdragon 8 chip. However, it is rumored that overheating issues prompted Qualcomm to assign the following generations to be manufactured by TSMC.

Nonetheless, according to Business Korea, the recent launch of the Snapdragon X Elite, extensively integrated with Microsoft’s CoPilot+ PC, has sparked greater demand, which has prompted Qualcomm to reassess its collaboration with Samsung.

According to a previous report by Wccftech, it is likely that the Samsung’s 2nm technology will be utilized for the Snapdragon 8 Gen 5 in the Galaxy S26 series.

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• [News] Samsung Fails to Secure Qualcomm’s 3nm Orders for the Coming Year, Dual Foundry Strategy Postponed

(Photo credit: Qualcomm)

JEDEC (the Solid State Technology Association) recently confirmed that the long-used SO-DIMM and DIMM memory standards will be replaced by CAMM2 for DDR6 (LPDDR6 included).

According to a report from WeChat account DRAMeXchange, the minimum frequency for DDR6 memory is 8800MHz, which can be increased to 17.6GHz, with a theoretical maximum of up to 21GHz, far surpassing that of DDR4 and DDR5 memory. CAMM2 is a brand new memory standard that also supports DDR6 standard memory, making it suitable for large PC devices like desktop PC. JEDEC expects to complete the preliminary draft of the DDR6 memory standard within this year, with the official version 1.0 expected by 2Q25 at the earliest, and specific products likely coming in 4Q25 or in 2026.

LPDDR6 will adopt a new 24-bit wide channel design, with a maximum memory bandwidth of up to 38.4GB/s, significantly higher than the existing LPDDR5 standard. The maximum rate for LPDDR6 can reach 14.4Gbps and the minimum rate is 10.667Gbps, matching the highest rate of LPDDR5x and far exceeding LPDDR5’s 6.7Gbps.

It is learned that a true CAMM2-standard LPDDR6, with a 32GB specification for example, costs about USD 500, which is five times the price of LPDDR5 (SO-DIMM/DIMM) memory.

Considering market adoption, the industry believes that the new CAMM2 standard adopted by DDR6 requires large-scale replacement of existing production equipment, which will bring about a new cost structure. Meanwhile, the evolution of new standards in the existing market will face high cost issue, which will restrict the large-scale adoption of DDR6 or LPDDR6.

Currently, upstream manufacturers like Samsung, SK Hynix, and Micron already have some memory products supporting the CAMM2 standard. Among downstream brand manufacturers, Lenovo and Dell also follow up and Dell reportedly has used CAMM2 memory boards in its enterprise product line in 2023.

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• [News] LPDDR6’s Bandwidth Expected to be Increased over 100%

(Photo credit: Samsung)