Samsung Electronics is ramping up its entry into the semiconductor glass substrate market by advancing its equipment procurement and installation to September, with trial production slated to begin in the fourth quarter, one quarter earlier than originally planned. According to a report from South Korean media outlet ETNews, Samsung Electronics aims to commence mass production of glass substrates for high-end System-in-Package (SiP) applications starting in 2026.

In order to manufacture highly complex multi-chiplet SiPs, Samsung has decided to expedite the trial production schedule at its Sejong plant in South Korea to gain more expertise in glass substrate manufacturing. Samsung’s competitor, Intel, also plans to offer packaging technology on glass substrates in the future.

Reportedly, Samsung Electronics plans to have all necessary equipment installed on the trial production line by September and commence operations in the fourth quarter. Partners for the trial production line include companies such as Philoptics, Chemtronics, Joongwoo M-Tech, and Germany’s LPKF, which will provide equipment components.

According to a report from Tom’s Hardware, Compared to traditional organic substrates, glass substrates offer significant advantages, including excellent flatness, which enhances exposure and focusing capabilities, as well as outstanding dimensional stability suitable for next-generation chip interconnects with multiple small chips. Additionally, glass substrates exhibit better thermal and mechanical stability, making them suitable for high-temperature durable applications in data centers.

Intel has been developing glass substrates for nearly a decade and plans to introduce commercial products by 2030. Intel believes that the characteristics of glass substrates will significantly increase interconnect density, which is crucial for efficient power transmission and signal routing in advanced SiP technology.

Previously, Intel also elaborated on its progress on the glass-based substrate packaging technology. According to Intel’s previous press release, glass substrates can tolerate higher temperatures, offer 50% less pattern distortion, and have ultra-low flatness for improved depth of focus for lithography as well as the dimensional stability needed for extremely tight layer-to-layer interconnect overlay.

As a result of these distinctive properties, a 10x increase in interconnect density is possible on glass substrates. Furthermore, improved mechanical properties of glass enable ultra-large form-factor packages with very high assembly yields.

Meanwhile, Absolics, a subsidiary of SKC America, aims to start production of glass substrates for customers as early as the second half of 2024.

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• [News] Samsung Bullish on Glass Substrate Applications, Setting Up Production Line for Mass Production Starting in 2026
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(Photo credit: Intel)

As Moore’s Law progresses, transistors are becoming smaller and denser, with more layers stacked on top of each other. This may require passing through 10 to 20 layers of stacking to provide power and data signals to the transistors below, leading to increasingly complex networks of interconnects and power lines. Simultaneously, as electrons transmit downward, IR drop phenomena occur, resulting in power loss.

Apart from power loss, the occupation of space by power supply lines is also a concern, which often occupies at least 20% of resources. Addressing the issue of signal network and power supply network resource contention to miniaturize components becomes a major challenge for chip designers. As per a report from TechNews, this has led the semiconductor industry to begin shifting power supply networks to the backside of chips.

• TSMC’s Super Rail Technology Set to Revolutionize Chip Efficiency with A16 Process Node Debut in 2025

Leading semiconductor foundry TSMC recently unveiled its A16 process at a technical forum in North America.

This new node not only accommodates more transistors, enhancing computational efficiency, but also reduces energy consumption. Of particular interest is the integration of the Super PowerRail architecture and nanosheet transistors in the A16 chip, driving the development of data center processors that are faster and more efficient.

Notably, TSMC’s A16 employs a different chip wiring manner, with power wires delivering electricity to transistors located beneath rather than above them, known as backside power supply, facilitating the production of more efficient chips.

In fact, one of the methods to optimize processors is to alleviate IR drop, a phenomenon that reduces the voltage received by the transistors on the chip, consequently affecting performance. The A16 wiring is less prone to voltage drops, simplifying power distribution and allowing for tighter chip packaging, aiming to accommodate more transistors to enhance computational capabilities.

Additionally, TSMC’s A16 process technology directly connects the power transmission lines to the source and drain of the transistor, which improves chip efficiency.

Using the Super PowerRail in A16, TSMC achieves an 10% higher clock speed or a 15% to 20% decrease in power consumption at the same operating voltage (Vdd) compared to N2P. Moreover, the chip density is increased by up to 1.10 times, supporting data center products.

• Intel’s PowerVia Set for Production on Intel 20A in 2024

Similar to TSMC’s Super PowerRail, Intel has also introduced its backside power delivery solution, PowerVia.

According to Intel, power lines typically occupy around 20% of the space on the chip surface, but PowerVia’s backside power delivery technology saves this space, allowing  more flexibility in the interconnect layers.

In addition, the Intel team previously created the Blue Sky Creek test chip to demonstrate the benefits of backside power delivery technology. Test results indicated that most areas of the chip achieved over 90% cell utilization, with a 30% platform voltage droop improvement, 6% frequency benefit, increased unit density, and potential cost reduction. The PowerVia test chip also exhibited excellent heat dissipation properties, aligning with expectations for higher power density as logic shrinks.

Furthermore, PowerVia is slated to be integrated into Intel Foundry Services (IFS), enabling faster achievement of product efficiency and performance enhancements for customer-designed chips.

According to official documentation from Intel, the tech giant plans to implement PowerVia on Intel 20A process technology along with the RibbonFET architecture for the full-surround gate transistor. Production readiness is expected in the first half of 2024, with initial steps being taken at the fabrication plant for future mass production of client ARL platforms.

• Samsung Plans to Implement SF1.4 Process by 2027

In addition to leading the transition to GAA transistor technology, Samsung, another competitor of TSMC, is also wielding its Backside Power Delivery Network as a key weapon in the pursuit of advanced processes.

According to a previous report from Samsung, Jung Ki-tae Jung, Chief Technology Officer of Samsung’s foundry division, announced plans to apply the backside power delivery technology to the 1.4-nanometer process by 2027.

Reports from Korean media outlet theelec indicate that compared to traditional front-end power delivery networks, Samsung’s backside power delivery network successfully reduces wafer area consumption by 14.8%, providing more space on the chip to accommodate additional transistors, thereby enhancing overall performance.

Additionally, wiring length is reduced by 9.2%, aiding in resistance reduction to allow more current flow, leading to lower power consumption and improved power transmission conditions. Samsung Electronics representatives noted that the mass production timeline for semiconductor chips adopting backside power delivery technology may vary depending on customer schedules, and Samsung is currently investigating customer demand for the application of this technology.

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• [News] More Complex than Intel’s? TSMC’s Super PowerRail – Elevating Chip Performance through Advanced Power Delivery
• [News] Battle of the Titans in the Angstrom Era – TSMC’s A16 Competes with Intel’s 14A and Samsung’s SF1.4

According to South Korean media outlet BusinessKorea’s report on May 2nd, NVIDIA is reported to be fueling competition between Samsung Electronics and SK Hynix, possibly in an attempt to lower the prices of High Bandwidth Memory (HBM).

The report on May 2nd has cited sources, indicating that the prices of the third-generation “HBM3 DRAM” have soared more than fivefold since 2023. For NVIDIA, the significant increase in the pricing of critical component HBM is bound to affect research and development costs.

The report from BusinessKorea thus accused that NVIDIA is intentionally leaking information to fan current and potential suppliers to compete against each other, aiming to lower HBM prices. On April 25th, SK Group Chairman Chey Tae-won traveled to Silicon Valley to meet with NVIDIA CEO Jensen Huang, potentially related to these strategies.

Although NVIDIA has been testing Samsung’s industry-leading 12-layer stacked HBM3e for over a month, it has yet to indicate willingness to collaborate. BusinessKorea’s report has cited sources, suggesting this is a strategic move aimed at motivate Samsung Electronics. Samsung only recently announced that it will commence mass production of 12-layer stacked HBM3e starting from the second quarter.

SK Hynix CEO Kwak Noh-Jung announced on May 2nd that the company’s HBM capacity for 2024 has already been fully sold out, and 2025’s capacity is also nearly sold out.  He mentioned that samples of the 12-layer stacked HBM3e will be sent out in May, with mass production expected to begin in the third quarter.

Kwak Noh-Jung further pointed out that although AI is currently primarily centered around data centers, it is expected to rapidly expand to on-device AI applications in smartphones, PCs, cars, and other end devices in the future. Consequently, the demand for memory specialized for AI, characterized by “ultra-fast, high-capacity and low-power,” is expected to skyrocket.

Kwak Noh-Jung also addressed that SK Hynix possesses industry-leading technological capabilities in various product areas such as HBM, TSV-based high-capacity DRAM, and high-performance eSSD. In the future, SK Hynix looks to provide globally top-tier memory solutions tailored to customers’ needs through strategic partnerships with global collaborators.

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• [News] HBM Craze Continues! SK Hynix Reports Sold Out for this Year, Next Year’s HBM Capacity Nearly Fully Booked
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(Photo credit: SK Hynix)

As the competition in advanced semiconductor chip manufacturing industry heats up, EUV lithography machine has been sought after by the market, attracting great attention across the industry.

Currently, Intel has taken the lead by purchasing ASML’s High-NA EUV lithography equipment and announced the completion of assembly recently. Samsung is also stepping up its efforts by partnering with Zeiss, a supplier of components for ASML’s EUV lithography machine, to deepen cooperation in the EUV field. At the same time, rumor has surfaced about the delivery of ASML’s second High-NA EUV lithography machine, though the buyer remains undisclosed.

• Samsung and Zeiss to Deepen EUV-Related Cooperation

According to South Korean media The Korea Herald report, Jay Y. Lee, the vice chairman of Samsung Electronics, recently met with Karl Lamprecht, President and CEO of Zeiss, along with other company executives in Germany.

During the meeting, both parties agreed to expand cooperation in EUV technology and cutting-edge semiconductor equipment development to enhance their competitiveness in the foundry and memory chip sectors. Through this collaboration, Samsung aims to advance next-generation semiconductor technology, optimize chip manufacturing processes, and improve the yield of advanced chips.

Zeiss also plans to invest KRW 48 billion by 2026 to establish a research and development center in South Korea as a way to strengthen strategic cooperation with South Korean companies including Samsung.

As a developer of optical and optoelectronic solutions, Zeiss serves as the exclusive supplier of components for ASML’s EUV lithography machines, with each machine containing over 30,000 components made by Zeiss. Zeiss holds more than 2,000 core patents about EUV technology, and its expertise can make a significant difference in the production of high-performance advanced chips.

In the future, Samsung Electronics and Zeiss will further expand their cooperation in EUV technology and related fields of advanced semiconductor equipment.

• ASML has Delivered the Second High NA EUV Lithography Machine?

Recently, Intel announced it has completed installation of the ASML High NA EUV lithography machine, which has now entered the optical system calibration phase. This represents the first High NA EUV lithography machine produced by ASML, valued at up to EUR 350 million. Intel plans to use this equipment to produce advanced process chips below 1.8nm.

In addition to Intel, companies such as TSMC, Samsung, and Micron have also placed orders for the High NA EUV lithography machine from ASML. ASML’s financial report for the first quarter of this year revealed a total of EUR 3.6 billion order intakes, with EURO 656 million from EUV lithography machine orders. ASML recently delivered its second equipment without revelation of the buyer.

The two High NA EUV lithography machines are insufficient to meet the market demand for advanced process chips. Therefore, ASML plans to manufacture more high-end lithography equipment in the future to address the continuously growing market demand.

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(Photo credit: ASML)

TSMC unveiled its angstrom-class A16 advanced process during the Company’s 2024 North America Technology Symposium on April 25, set to be mass-produced in 2026. Not only is this earlier than competitors like Intel’s 14A and Samsung’s SF14, both slated for 2027 production, but TSMC also emphasized that the A16 does not require the use of High-NA EUV, making it more cost-competitive.

TSMC’s A16 to Lead Competitors in Production Time and Cost

According to TSMC, the A16 advanced process, combining Super PowerRail and nanosheet transistors, is set for mass production in 2026. Super PowerRail relocates power networks to the backside of wafers, freeing up more space on the frontside for signal networks, enhancing logic density and performance. This is ideal for High-Performance Computing (HPC) products with complex signal routing and dense power networks.

Compared to TSMC’s N2P process, the A16 offers an 8% to 10% speed increase at the same Vdd (operating voltage), a 15% to 20% reduction in power consumption at the same speed, and a density increase of up to 1.1 times, supporting data center products.

Photo credit: TSMC

Additionally, as AI chip companies are eager to optimize designs to leverage the full potential of TSMC’s processes, as per a report from Reuters, TSMC doesn’t believe that ASML’s latest High-NA EUV is necessary for producing A16 process chips.

Furthermore, TSMC showcased the Super Power Rail architecture, slated to be operational in 2026, which delivers power from the backside of the chip, aiding in the accelerated operation of AI chips.

Intel 14A Extends ‘5 Nodes in 4 Years’ Strategy

In February, Intel unveiled its 14A process, which would be after its “5 Nodes in 4 Years” strategy. After integrating High-NA EUV production, Intel 14A is expected to improve energy efficiency by 15% and increase transistor density by 20% compared to Intel 18A.

The enhanced version, Intel 14A-E, will further boost energy efficiency by 5% based on Intel 14A. According to the plan, Intel 14A is set for mass production as early as 2026, while Intel 14A-E is slated for 2027.

Photo credit: Intel

Intel recently announced the completion of the industry’s first commercial High-NA EUV lithography tool assembly. The ASML TWINSCAN EXE:5000 High-NA EUV lithography tool is undergoing multiple calibrations and is scheduled to be operational in 2027 for Intel’s 14A process.

Intel emphasizes that when the High-NA EUV lithography tool is combined with its other leading process technologies, it reduces print size by 1.7 times compared to existing EUV machines. This reduction in 2D dimensions increases density by 2.9 times, aiding Intel in advancing its process roadmap.

Samsung SF1.4 Enhances Performance and Power Efficiency with Nanosheet Addition

Photo credit: Samsung

Compared to TSMC and Intel, Samsung’s progress in the angstrom era seems somewhat lagging. Two years ago at the Samsung Foundry Forum 2022, Samsung unveiled its advanced process roadmap, with the angstrom-level SF1.4 (1.4 nanometers) set for mass production in 2027.

Last October, Samsung’s Vice President of Foundry, Jeong Gi-Tae, reportedly told the Korean media outlet The Elec that Samsung has announced its upcoming SF1.4 (1.4-nanometer class) process technology, which would increase the number of nanosheets from 3 to 4. This move is expected to bring significant benefits in chip performance and power consumption

Samsung announced the mass production of SF3E (3nm GAA) in June 2022, introducing a new Gate-All-Around (GAA) architecture. This year, they unveiled the second-generation 3nm process, SF3 (3nm GAP), utilizing the second-generation Multi-Bridge Channel Field Effect Transistor (MBCFET) to optimize performance based on the SF3E foundation.

Additionally, they introduced the performance-enhanced SF3P (3GAP+), suitable for manufacturing high-performance chips. By 2025, Samsung plans to scale up production of the SF2 (2nm) process, followed by mass production of the SF1.4 (1.4nm) process in 2027.

Reportedly, Samsung aims to increase the number of nanosheets per transistor to enhance drive current and improve performance. More nanosheets allow higher current to pass through the transistor, enhancing switching capability and operational speed.

Moreover, more nanosheets offer better control over current, helping to reduce leakage and lower power consumption. Improving current control means transistors generate less heat.

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