TSMC unveiled its angstrom-class A16 advanced process during the Company’s 2024 North America Technology Symposium on April 25, set to be mass-produced in 2026. Not only is this earlier than competitors like Intel’s 14A and Samsung’s SF14, both slated for 2027 production, but TSMC also emphasized that the A16 does not require the use of High-NA EUV, making it more cost-competitive.

TSMC’s A16 to Lead Competitors in Production Time and Cost

According to TSMC, the A16 advanced process, combining Super PowerRail and nanosheet transistors, is set for mass production in 2026. Super PowerRail relocates power networks to the backside of wafers, freeing up more space on the frontside for signal networks, enhancing logic density and performance. This is ideal for High-Performance Computing (HPC) products with complex signal routing and dense power networks.

Compared to TSMC’s N2P process, the A16 offers an 8% to 10% speed increase at the same Vdd (operating voltage), a 15% to 20% reduction in power consumption at the same speed, and a density increase of up to 1.1 times, supporting data center products.

Photo credit: TSMC

Additionally, as AI chip companies are eager to optimize designs to leverage the full potential of TSMC’s processes, as per a report from Reuters, TSMC doesn’t believe that ASML’s latest High-NA EUV is necessary for producing A16 process chips.

Furthermore, TSMC showcased the Super Power Rail architecture, slated to be operational in 2026, which delivers power from the backside of the chip, aiding in the accelerated operation of AI chips.

Intel 14A Extends ‘5 Nodes in 4 Years’ Strategy

In February, Intel unveiled its 14A process, which would be after its “5 Nodes in 4 Years” strategy. After integrating High-NA EUV production, Intel 14A is expected to improve energy efficiency by 15% and increase transistor density by 20% compared to Intel 18A.

The enhanced version, Intel 14A-E, will further boost energy efficiency by 5% based on Intel 14A. According to the plan, Intel 14A is set for mass production as early as 2026, while Intel 14A-E is slated for 2027.

Photo credit: Intel

Intel recently announced the completion of the industry’s first commercial High-NA EUV lithography tool assembly. The ASML TWINSCAN EXE:5000 High-NA EUV lithography tool is undergoing multiple calibrations and is scheduled to be operational in 2027 for Intel’s 14A process.

Intel emphasizes that when the High-NA EUV lithography tool is combined with its other leading process technologies, it reduces print size by 1.7 times compared to existing EUV machines. This reduction in 2D dimensions increases density by 2.9 times, aiding Intel in advancing its process roadmap.

Samsung SF1.4 Enhances Performance and Power Efficiency with Nanosheet Addition

Photo credit: Samsung

Compared to TSMC and Intel, Samsung’s progress in the angstrom era seems somewhat lagging. Two years ago at the Samsung Foundry Forum 2022, Samsung unveiled its advanced process roadmap, with the angstrom-level SF1.4 (1.4 nanometers) set for mass production in 2027.

Last October, Samsung’s Vice President of Foundry, Jeong Gi-Tae, reportedly told the Korean media outlet The Elec that Samsung has announced its upcoming SF1.4 (1.4-nanometer class) process technology, which would increase the number of nanosheets from 3 to 4. This move is expected to bring significant benefits in chip performance and power consumption

Samsung announced the mass production of SF3E (3nm GAA) in June 2022, introducing a new Gate-All-Around (GAA) architecture. This year, they unveiled the second-generation 3nm process, SF3 (3nm GAP), utilizing the second-generation Multi-Bridge Channel Field Effect Transistor (MBCFET) to optimize performance based on the SF3E foundation.

Additionally, they introduced the performance-enhanced SF3P (3GAP+), suitable for manufacturing high-performance chips. By 2025, Samsung plans to scale up production of the SF2 (2nm) process, followed by mass production of the SF1.4 (1.4nm) process in 2027.

Reportedly, Samsung aims to increase the number of nanosheets per transistor to enhance drive current and improve performance. More nanosheets allow higher current to pass through the transistor, enhancing switching capability and operational speed.

Moreover, more nanosheets offer better control over current, helping to reduce leakage and lower power consumption. Improving current control means transistors generate less heat.

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• [News] The Imminent Arrival of 2-Nanometer Advanced Process
• [News] Intense Competition with Samsung and Intel in Advanced Processes; TSMC Speeds Up 2nm Progress

Henri Richard, head of Rapidus Design Solutions, the US subsidiary of Japan’s semiconductor foundry startup Rapidus, and former Chief Marketing Officer at processor giant AMD, indicates that Rapidus aims to position itself as a filler of market gaps during the interview with global media The Register.

Rapidus Design Solutions, established by Rapidus in this month, is expected to bolster ties with US semiconductor design companies and wafer manufacturing technology providers like IBM. Henri Richard reportedly notes that the AI boom is boosting the advanced semiconductor foundry market, albeit with understated demand and ongoing capacity constraints. Thus, in this market trend, he asserts that even if these technologies don’t necessarily confer a competitive edge, the limitations in capacity alone should suffice to ensure Rapidus’ success.

Established in August 2022, Rapidus was jointly founded by eight Japanese companies, including Toyota, Sony, NTT, NEC, Softbank, Denso, Kioxia (formerly Toshiba Memory Corporation), and Mitsubishi UFJ, who invested collectively in its establishment. As per Rapidus’ plan, they aim to commence mass production of 2-nanometer process technology in 2027, significantly lagging behind major global players like TSMC, Intel, and Samsung.

TSMC and Samsung previously planned to mass-produce 2nm chips in 2025, while Intel is anticipated to be the first to achieve commercialization of 2nm chips. Industry sources cited by the The Register’s report also view this timing as unfavorable for Rapidus.

However, Henri Richard believes that the semiconductor process technology has reached a turning point. Assessing the success of suppliers solely based on production timelines is narrow-minded; competitiveness stems from various factors beyond production schedules.

Based on these factors, Rapidus positions itself as a fill-in player in the advanced manufacturing market, targeting small AI chip design companies as its primary market. While competitors focus on serving large clients, Rapidus aims to win over these smaller clients by offering comprehensive support services. By serving numerous small chip design companies, Rapidus can better understand the specific needs of AI chip users, rather than insisting on the latest process technology for all chips.

Henri Richard emphasizes that Rapidus itself has limited scale and cannot initially serve too many clients simultaneously. It is expected that Rapidus’s initial client base will not exceed 6 companies, allowing them to accumulate experience and capabilities.

Although there are geopolitical issues currently, establishing facilities in the US is not on Rapidus’s immediate agenda. Meanwhile, Japan represents a relatively favorable geographic location for Rapidus, offering clients a risk-diversification option.

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• [News] Global Acceleration in the Construction of 2nm Wafer Plants
• [News] Rapidus, the First 2nm Client, to Manufacture AI Chips for Tenstorrent

(Photo credit: Rapidus)

According to a report from Korean media outlet viva100, Samsung has signed a new USD 3 billion agreement with processor giant AMD to supply HBM3e 12-layer DRAM for use in the Instinct MI350 series AI chips. Reportedly, Samsung has also agreed to purchase AMD GPUs in exchange for HBM products, although details regarding the specific products and quantities involved remain unclear.

Earlier market reports indicated that AMD plans to launch the Instinct MI350 series in the second half of the year as an upgraded version of the Instinct MI300 series. The MI350 series is reportedly expected to adopt TSMC’s 4-nanometer process, delivering improved computational performance with lower power consumption. The inclusion of 12-layer stacked HBM3e memory will enhance both bandwidth and capacity.

In October 2023, at Samsung Memory Tech Day 2023, Samsung announced the launch of a new HBM3e codenamed “Shinebolt.” In February of this year, Samsung unveiled the industry’s first HBM3e 12H DRAM, featuring 12 layers and a capacity of 36GB, marking the highest bandwidth and capacity HBM product to date. Samsung has provided samples and plans to commence mass production in the second half of the year.

Samsung’s HBM3e 12H DRAM offers up to 1280GB/s bandwidth and 36GB capacity, representing a 50% increase compared to the previous generation of eight-layer stacked memory. Advanced Thermal Compression Non-Conductive Film (TC NCF) technology enables the 12-layer stack to meet HBM packaging requirements while maintaining chip height consistency with eight-layer chips.

Additionally, optimizing the size of chip bumps improves HBM thermal performance, with smaller bumps located in signal transmission areas and larger bumps in heat dissipation areas, contributing to higher product yields.

The adoption of HBM3e 12-layer DRAM over HBM3e 8-layer DRAM has shown an average speed improvement of 34% in AI applications, with inference service users increasing by over 11.5 times.

In view of this matter, industry sources cited by the report from TechNews has indicated that this deal is separate from negotiations between AMD and Samsung Foundry for wafer production. AMD plans to assign a portion of new CPUs/GPUs to Samsung for manufacturing, which is unrelated to this specific transaction.

Read more

• [News] Samsung Reportedly Establishes New HBM Team, Looking to Improve AI Chip Yield
• [News] Memory Manufacturers Vie for HBM3e Market

(Photo credit: Samsung)

Samsung Display (SDC), a subsidiary of Samsung, has been developing its own OLEDoS (OLED on Silicon) technology. However, there are reports now indicating that Samsung’s smartphone division plans to adopt Sony’s OLEDoS technology for integration into Samsung’s XR devices.

According to the Korean media “The Elec,” Samsung’s MX division has decided to utilize the technology from Sony instead of the technology from the group’s SDC, reflecting Samsung’s need for a new technology manager to oversee new semiconductor devices (referring to electronic components, such as OLEDs and transistors).

This newly created position for device development must oversee the technological advancement of all of Samsung’s electronic businesses, including Samsung MX, DS (chip division), displays, and motors. If Samsung’s subsidiaries had collaborated closely from the outset, then Samsung’s MX division might have adopted SDC’s technology instead of Sony’s. A similar situation has also occurred with the glass substrate developed by Samsung Electronics.

“The Elec” believes it is strange that SDC has not collaborated with the group’s companies on OLEDoS technology, as SDC has expertise in glass processing. This highlights a lack of clear roles and responsibilities within Samsung, which is a significant waste of internal resources.

OLEDoS and glass substrate microdisplays require close cooperation between departments such as semiconductors, displays, circuit boards, and display glass processing technology. If these departments are well integrated, it could bring opportunities for Samsung, as the company has departments capable of handling all related technologies.

However, the current situation does not reflect this. SDC initiated the M project at the end of 2022, aimed at developing OLEDoS and LED on Silicon technology. But SDC losing to Sony now means the former will lose valuable production experience.

(Photo credit: Samsung)

As AI semiconductor competition intensifies, the wafer foundry industry faces new challenges due to stagnant demand and excess capacity. The battle for dominance in the high-bandwidth memory (HBM) market is also escalating.

According to Business Korea, Samsung has extended the operation time of its Taylor plant from the end of 2024 to 2026, possibly adjusting the investment pace in consideration of the foundry market.

Regarding the global wafer foundry industry outlook for this year, TSMC President C.C. Wei stated that the growth of the global foundry industry this year has been revised from the previous earnings call of 20% to mid-teens.

Currently, TSMC’s two fabs in Arizona, USA, are scheduled to commence production in 2025 and 2028, respectively; the Kumamoto fab in Japan has started operations in February, and the second fab will start production before 2027. Intel, on the other hand, plans to establish new foundries in the United States, Europe, and Israel. The activation of these new fabs has raised concerns in the market about oversupply issues.

Contrastingly, in the HBM market, crucial for AI chips, SK Hynix and TSMC have formed an alliance, intensifying the competition between this alliance and Samsung.

SK Hynix announced on April 19th that the company has recently signed a memorandum of understanding with TSMC for collaboration to produce next-generation HBM and enhance logic and HBM integration through advanced packaging technology. The company plans to proceed with the development of HBM4, or the sixth generation of the HBM family, slated to be mass produced from 2026, through this initiative.

Looking at Samsung’s developments in the HBM, Samsung Electronics successfully developed the industry’s first highest-capacity 12-layer HBM3E in February, attempting to regain market dominance. In the second quarter, along with the 8-layer product, it will supply to Nvidia. The next goal is to launch the 16-layer HBM4.

Per TrendForce’s data, the three major HBM manufacturers held market shares are as follows: In 2023, SK Hynix and Samsung each held around 47.5%, while Micron’s share was roughly 5%. Still, forecasts indicate that SK Hynix’s market share in 2024 will increase to 52.5%, while Samsung’s will decrease to 42.4%.

In line with the same report from Business Korea, despite the decline in foundry demand, Samsung Electronics and SK Hynix’s profit prospects are expected to improve compared to last year.

As per estimates cited in the report from investment institutions, SK Hynix’s first-quarter revenue is expected to reach 12.1021 trillion won, with an operating profit of 1.7654 trillion won, and the operating profit for the entire year of 2024 is expected to exceed 21 trillion won; Samsung Electronics’ DS division’s performance is improving, with the first-quarter operating profit expected to be between 700 billion and 1.8 trillion won, and the overall operating profit for 2024 is expected to be around 35 trillion won.

(Photo credit: SK Hynix)