Amid the overwhelming wave of Artificial Intelligence, the importance of advanced process chips is becoming increasingly prominent. Currently, the 3nm process is the most advanced node in the industry. Meanwhile, manufacturers such as TSMC, Samsung, Intel, and Rapidus are actively promoting the construction of 2nm wafer fabs. TSMC and Samsung previously planned to mass-produce 2nm chips in 2025, while Rapidus to begin trial production in 2025.

2nm Wafer Fabs to Complete Construction as Soon as this Year?

Recently, the Semiconductor Equipment and Materials International (SEMI) announced that it is expected that both TSMC and Intel will potentially complete the construction of 2nm wafer fabs by the end of this year.

Intel is anticipated to be the first to achieve commercialization of 2nm chips. The Intel PC CPU Arrow Lake product will utilize the 2nm process node. TSMC’s 2nm process is expected to be applied in Apple’s iPhone AP chips. Subsequently, TSMC’s 2nm capacity will soar up.

According to a report from Commercial Times the installation of equipment for TSMC’s 2nm process is accelerating. TSMC’s Fab20 P1 plant in Hsinchu, Baoshan is scheduled to install equipment in April this year, with pilot production expected to commence in 2H24 and small-scale production in 2Q25.

As for Intel, ASML already delivered the world’s first High Numerical Aperture (NA) EUV EXE:5200 to Intel in late 2023, supporting the latter in producing 2nm chips. Later, Intel kicked-start the calibration of lithography machine, which has been well on track.

Samsung and Rapidus all Set to Move

In terms of Samsung, its previously announced technology roadmap indicates that it will first mass-produce 2nm process chips for mobile terminals starting in 2025, followed by high-performance computing (HPC) products in 2026. It plans to expand to automotive chips by 2027.

Rapidus is setting up a 2nm chip fab in Chitose City, Hokkaido, Japan. Its pilot production line is scheduled to start operation in April 2025, aiming to commence mass production in 2027.

Recently, it’s reported that in order to promote the development of advanced wafer fabs in Japan, several Japanese manufacturers will supply products to Rapidus. Among them, Dai Nippon Printing (DNP) will begin mass production of masks for 2nm chips at its Fukuoka plant and other operations in Japan in 2027, which will be provided to Rapidus.

In addition to DNP, Japanese company TOPPAN Holdings is also collaborating with IBM to develop masks for 2nm chips and achieve mass production by 2026, and Rapidus is reportedly the purchaser. Moreover, companies like Tokyo Ohka Kogyo (TOK), JSR, Shin-Etsu Chemical are also expected to be the suppliers of Rapidus.

1nm Chip Plans Brought to Light

Following 2nm, 1nm chip will be the next target for wafer fabs. In light of manufacturers’ plans, the industry is expected to see mass production of 1nm-level chips from 2027 to 2030.

TSMC plans to reach the A14 node (1.4nm) in 2027 and the A10 node (1nm) in 2030. Recent reports from Economic Daily News indicated that TSMC intends to establish a factory in the Science Park of Taibao City, Chiayi County in central Taiwan to produce 1nm chips.

Samsung anticipates to launch the 1.4nm process by late 2027. It is reported that Samsung’s SF1.4 (1.4 nm) process can increase the number of nanosheets from 3 to 4, which is expected to significantly improve performance and power consumption.

Intel’s latest foundry roadmap shows that the Intel 14A (1.4nm-level) node will put into production in 2026, and Intel 10A (1nm-level) will start development or production in late 2027.

Samsung Electronics Co. has recently established a HBM team within its memory division, with the goal of enhancing yield during the development of the sixth-generation AI memory HBM4 and the AI accelerator Mach-1.

According to a report of the Korea Economic Daily (KED) citing industry sources on March 29th, Samsung’s HBM team is primarily responsible for the research, development, and sales of DRAM and NAND flash memory. Samsung’s Executive Vice President and Chief of DRAM Product and Technology, Hwang Sang-joon, will lead the new team. This marks the second team focused on HBM since Samsung initiated its HBM task force in January.

Per KED’s report, Samsung is stepping up its efforts in hopes of surpassing SK Hynix, the leader in the advanced HBM field. In 2019, Samsung dissolved its HBM team due to a mistaken belief that the market would not see significant growth.

Per a previous TrendForce press release, the three major original HBM manufacturers held market shares as follows in 2023: SK Hynix and Samsung were both around 46-49%, while Micron stood at roughly 4-6%.

To vie for dominance in the AI chip market, Samsung is pursuing a “two-track” strategy by concurrently developing two cutting-edge memory chips: HBM and Mach-1.

According to TrendForce’s report, SK Hynix led the way with its HBM3e validation in the first quarter, closely followed by Micron, which plans to start distributing its HBM3e products toward the end of the first quarter, in alignment with NVIDIA’s planned H200 deployment by the end of the second quarter.

Samsung, slightly behind in sample submissions, is expected to complete its HBM3e validation by the end of the first quarter, with shipments rolling out in the second quarter.

According to the same report from KED, Samsung is also gearing up to develop the next-generation accelerator, “Mach-2,” tailored for AI inference. According to Kyung on March 29th, Samsung must expedite the development of Mach-2 as there is strong interest from customers in this regard.

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• [News] Memory Manufacturers Vie for HBM3e Market
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(Photo credit: Samsung)

Recently, South Korean media Alphabiz reported that Samsung may exclusively supply 12-layer HBM3e to NVIDIA.

The report indicates NVIDIA is set to commence large-scale purchases of Samsung Electronics’ 12-layer HBM3e as early as September, who will exclusively provide the 12-layer HBM3e to NVIDIA.

NVIDIA CEO Jensen Huang, as per Alphabiz reported, left his signature “Jensen Approved” on a physical 12-layer HBM3e product from Samsung Electronics at GTC 2024, which seems to suggest NVIDIA’s recognition of Samsung’s HBM3e product.

HBM is characterized by its high bandwidth, high capacity, low latency, and low power consumption. With the surge in artificial intelligence (AI) industry, the acceleration of AI large-scale model applications has driven the continuous growth of demand in high-performance memory market.

According to TrendForce’s data, HBM market value accounted for approximately 8.4% of the overall DRAM industry in 2023, and this percentage is projected to expand to 20.1% by the end of 2024.

Senior Vice President Avril Wu notes that by the end of 2024, the DRAM industry is expected to allocate approximately 250K/m (14%) of total capacity to producing HBM TSV, with an estimated annual supply bit growth of around 260%.

HBM3e: Three Major Original Manufacturers Kick off Fierce Rivalry

Following the debut of the world’s first TSV HBM product in 2014, HBM memory technology has now iterated to HBM3e after nearly 10 years of development.

From the perspective of original manufacturers, competition in the HBM3e market primarily revolves around Micron, SK Hynix, and Samsung. It is reported that these three major manufacturers already provided 8-hi (24GB) samples in late July, mid-August, and early October 2023, respectively. It is worth noting that this year, they have kicked off fierce competition in the HBM3e market by introducing latest products.

On February 27th, Samsung announced the launch of its first 12-layer stacked HBM3e DRAM–HBM3e 12H, which marks Samsung’s largest-capacity HBM product to date, boasting a capacity of up to 36GB. Samsung stated that it has begun offering samples of the HBM3e 12H to customers and anticipates starting mass production in the second half of this year.

In early March, Micron announced that it had commenced mass production of its HBM3e solution. The company stated that the NVIDIA H200 Tensor Core GPU will adopt Micron’s 8-layer stacked HBM3e memory with 24GB capacity and shipments are set to begin in the second quarter of 2024.

On March 19th, SK Hynix announced the successful large-scale production of its new ultra-high-performance memory product, HBM3e, designed for AI applications. This achievement symbolizes the world’s first supply of DRAM’s highest-performance HBM3e in existence to customers.

A previous report from TrendForce has indicated that, starting in 2024, the market’s attention will shift from HBM3 to HBM3e, with expectations for a gradual ramp-up in production through the second half of the year, positioning HBM3e as the new mainstream in the HBM market.

TrendForce reports that SK hynix led the way with its HBM3e validation in the first quarter, closely followed by Micron, which plans to start distributing its HBM3e products toward the end of the first quarter, in alignment with NVIDIA’s planned H200 deployment by the end of the second quarter.

Samsung, slightly behind in sample submissions, is expected to complete its HBM3e validation by the end of the first quarter, with shipments rolling out in the second quarter. With Samsung having already made significant strides in HBM3 and its HBM3e validation expected to be completed soon, the company is poised to significantly narrow the market share gap with SK Hynix by the end of the year, reshaping the competitive dynamics in the HBM market.

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(Photo credit: SK Hynix)

Amid the AI boom driving a surge in demand for advanced packaging, South Korean semiconductor giant Samsung Electronics is aggressively entering the advanced packaging arena. On the 20th, it announced its ambitions to achieve record-high revenue in advanced packaging this year, aiming to surpass the USD 100 million mark.

According to reports from Reuters and The Korea Times, Samsung’s annual shareholders’ meeting took place on March 20th.

During the meeting, Han Jong-hee, the vice chairman of the company, stated as follows: “Although the macroeconomic environment is expected to be uncertain this year, we see an opportunity for increased growth through next-generation technology innovation.”

“Samsung plans to apply AI to all devices, including smartphones, foldable devices, accessories and extended reality (XR), to provide customers with a new experience where generative AI and on-device AI unfold,” Han added.

Samsung established the Advanced Package Business Team under the Device Solutions business group in December last year. Samsung Co-CEO Kye-Hyun Kyung stated that he expects the results of Samsung’s investment to come out in earnest from the second half of this year.

Kyung further noted that for a future generation of HBM chips called HBM4, likely to be released in 2025 with more customised designs, Samsung will take advantage of having memory chips, chip contract manufacturing and chip design businesses under one roof to satisfy customer needs.

According to a previous report from TrendForce, Samsung led the pack with the highest revenue growth among the top manufacturers in Q4 as it jumped 50% QoQ to hit $7.95 billion, largely due to a surge in 1alpha nm DDR5 shipments, boosting server DRAM shipments by over 60%. In the fourth quarter of last year, Samsung secured a market share of 45.5% in DRAM chips.

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• [News] Samsung Accelerates 3D Packaging with Hybrid Bonding Production Line in Korean Advanced Packaging Hub
• DRAM Industry Sees Nearly 30% Revenue Growth in 4Q23 Due to Rising Prices and Volume, Says TrendForce

(Photo credit: Samsung)

According to sources cited by Reuters,  TSMC is reportedly considering plans to establish a production line for its CoWoS technology in Japan. However, TSMC has yet to make any further decisions, and they have declined to comment on the matter.

CoWoS is an advanced packaging technology that stacks chips to enhance computing power, reduce energy consumption, and save space. Currently, TSMC’s CoWoS production capacity is entirely located in Taiwan.

With the booming development of artificial intelligence, global demand for advanced semiconductor packaging has surged, prompting chip suppliers like TSMC, Samsung, and Intel to strengthen their advanced packaging capabilities.

Previously, TSMC’s CEO, C.C. Wei, stated that the company plans to double its CoWoS output by the end of 2024 and further increase it in 2025. With TSMC recently completing the first phase of construction for its Kumamoto fab in Japan and announcing plans for the second phase, which will involve collaboration with Japanese companies SONY Semiconductor Solutions and Toyota Motor Corporation, with a total investment exceeding USD 20 billion and utilizing 6/7-nanometer advanced processes.

However, Joanne Chiao, an analyst at market research firm TrendForce, suggests that if TSMC establishes advanced packaging capacity in Japan, it may face limitations in scale. It remains unclear how much demand there is in Japan for CoWoS packaging, but most of TSMC’s CoWoS customers are currently in the United States.

Additionally, sources cited by Reuters’ report indicate that TSMC’s competitor, Intel, is also considering establishing an advanced packaging research facility in Japan to deepen ties with local chip supply chain companies.

Meanwhile, Samsung, another competitor of TSMC, is setting up advanced packaging research facilities in Yokohama, Japan, with government support. Furthermore, Samsung is in discussions with Japanese and other companies regarding material procurement, preparing to launch its packaging technology similar to that used by SK Hynix.

Regarding the development of the semiconductor industry in Japan, as mentioned in a previous report from TrendForce, Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

However, the looming shortage of semiconductor talent in Japan is a concern. In response, there are generous subsidy programs for talent development. Japan is strategically positioning itself to reclaim its former glory in the world of semiconductors.

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• [News] Subsidies to TSMC from Japan and China Increase Over Fivefold Annually
• [News] High Efficiency in TSMC Kumamoto Plant Construction Sets Stage for Potential Advanced Packaging Investment in Japan

(Photo credit: TSMC)