Amidst the AI frenzy, HBM has become a focal point for major semiconductor manufacturers, and another storage giant is making new moves.

According to Korean media “THE ELEC”, Samsung Electronics plans to establish an HBM development office to enhance its competitiveness in the HBM market. The size of the team has not been determined yet, but Samsung’s HBM task force is expected to undergo upgrades.

The report indicates that if the task force is upgraded to a development office, Samsung will then establish specialized design and solution teams for HBM development. The head of the development office will be appointed from among vice president-level personnel.

In terms of research and development progress, the three major manufacturers have all advanced to the stage of HBM3e.

Regarding Samsung, in February, the company just released its first 36GB HBM3e 12H DRAM, which is currently Samsung’s largest capacity HBM product. Presently, Samsung has begun providing samples of HBM3e 12H to customers, with mass production expected to commence in the latter half of this year.

On the other hand, Micron Technology has announced the commencement of mass production of high-frequency memory “HBM3e,” which will be utilized in NVIDIA’s latest AI chip, the “H200” Tensor Core graphics processing unit (GPU). The H200 is scheduled for shipment in the second quarter of 2024.

Another major player, SK Hynix, as per Business Korea, plans to begin mass production of HBM3e in the first half of 2024.

In terms of production capacity, both SK Hynix and Micron Technology have previously disclosed that HBM production capacity is fully allocated. This indicates a strong market demand for HBM, reaffirming manufacturers’ determination to expand production.

As per previous report by Bloomberg, SK Hynix plans to invest an additional USD 1 billion in advanced packaging for HBM. The company stated in its recent financial report that it intends to increase capital expenditures in 2024 and shift production focus to high-end storage products such as HBM.

The capacity for HBM is expected to more than double compared to last year. From a demand perspective, it is anticipated that over 60% of future demand for HBM will stem from the primary application of AI servers.

Read more

• [News] SK Hynix Reportedly Invests USD 1 Billion in Advanced Packaging to Strengthen HBM Chip Leadership
• High-End AI Server Demand from North America’s Top Four CSPs Expected to Exceed 60% in 2024, Says TrendForce

(Photo credit: Samsung)

Recently, IC design company Marvell announced an expansion of its long-term partnership with TSMC to include 2-nanometer technology. They will collaborate on developing the industry’s first 2-nanometer semiconductor production platform optimized for accelerating infrastructure.

Currently, the most advanced production technology in the industry is the 3-nanometer process, manufactured by Samsung Electronics and TSMC. With Intel securing the first ASML lithography machine and updating its latest manufacturing roadmap, and with the increasing collaboration between Rapidus and IBM, the competition for the 2-nanometer advanced process has significantly expanded to include TSMC, Intel, Samsung and  Rapidus.

• Marvell

According to Marvell’s press release, it has stated that Marvell has transitioned from a follower to a leader in integrating advanced node technology into silicon infrastructure.

Marvell first bringing advanced node technology to infrastructure silicon with its 5nm platform, followed by the release of several 5-nanometer designs and the profolio of the first silicon infrastructure product lineup based on TSMC’s 3-nanometer process.

“Tomorrow’s artificial intelligence workloads will require significant and substantial gains in performance, power, area, and transistor density. The 2nm platform will enable Marvell to deliver highly differentiated analog, mixed-signal, and foundational IP to build accelerated infrastructure capable of delivering on the promise of AI,” said Sandeep Bharathi, chief development officer at Marvell.

• TSMC

TSMC commenced mass production of its 3-nanometer process in 2022, with profitability realized starting from the third quarter of 2023. By the fourth quarter of 2023, the 3-nanometer process contributed to 15% of wafer revenue, and its revenue share has been steadily increasing.

According to TrendForce, the foundry market is expected to grow by 7% in 2024, largely attributed to TSMC’s ramp-up of its 3-nanometer process. This has further increased TSMC’s market share.

During the earnings call in the fourth quarter of 2023, TSMC announced that its 2-nanometer process (N2) would utilize Nanosheet transistor structures. It is anticipated that N2 will commence mass production in 2025, leading the industry in terms of density and energy efficiency.

The N2 backside power delivery solution is slated for release in the latter half of 2025 and is expected to enter mass production in 2026, primarily targeting the High-Performance Computing (HPC) sector.

Furthermore, due to the current high demand for 2-nanometer processes from all AI innovators worldwide surpassing that for 3-nanometer processes, almost all AI innovators are collaborating with TSMC on 2-nanometer process technology. The main applications are primarily focused on high-performance computing (HPC) and smartphones.

Consequently, TSMC has announced plans to expand its production capacity for 2-nanometer processes. Originally, two 2-nanometer fabs were planned for the Kaohsiung facility, but now consideration is being given to constructing a third 2-nanometer fab.

• Samsung

Samsung commenced mass production of its 3-nanometer process in June 2022. According to the latest industry reports, Samsung has developed a “second-generation 3-nanometer” process, renamed as “2-nanometer”, with plans for mass production before the end of this year.

At the 2023 Samsung Foundry Forum, Samsung Electronics unveiled the latest roadmap for its 2-nanometer process. Samsung Electronics President and Head of Foundry Business, Siyoung Choi, disclosed that Samsung will first mass-produce 2-nanometer chips for mobile terminals starting from 2025. Subsequently, in 2026, the technology will be applied to high-performance computing (HPC) products, followed by expansion to automotive chips by 2027.

Unlike TSMC, which opted for Gate-All-Around (GAA) structure at the outset of its 2-nanometer process, Samsung has been utilizing GAA structure since its 3-nanometer process. This suggests that Samsung may have more experience in new structures compared to TSMC, thus giving Samsung an advantage in its 2-nanometer node.

In the past, when Samsung Electronics transitioned from 7-nanometer to 5-nanometer process technology in 2020, the second generation 7-nanometer process technology was renamed as 5-nanometer process technology.

Samsung Electronics’ 7-nanometer process technology became the world’s first to use Extreme Ultraviolet (EUV) lithography in 2019, making it more stable and enabling the company to further shrink transistor sizes. This was also the reason for renaming the second generation 7-nanometer process to 5-nanometer process at that time.

A report from the Business Korea has indicated that Samsung Electronics recently secured an order from the Japanese AI startup Preferred Networks (PFN) to produce semiconductors based on the 2-nanometer process.

It is reported that PFN has been collaborating with TSMC since 2016, but this year, it has decided to produce the next generation of AI chips at Samsung’s 2-nanometer node. According to the agreement, Samsung will utilize its latest 2-nanometer chip fab technology to manufacture AI accelerators and other AI chips for PFN.

• Intel

As per Intel’s previously announced plans, the company aims to catch up with and surpass TSMC by 2024 or 2025. At this year’s “Direct Connect” conference hosted by Intel Foundry Services, the company unveiled its latest technological roadmap.

Intel has reported that its primary product, Clearwater Forest, which is under the 18A process, has been completed and is set for production in 2025. Intel’s 18A process is often compared with TSMC’s N2 (2-nanometer) and N3P (3-nanometer) processes in terms of performance, with each company advocating for its own advantages.

Intel CEO Pat Gelsinger emphasizes that both 18A and N2 utilize GAA transistors (RibbonFET), but the 1.8-nanometer node will adopt BSPND, a backside power delivery technology that optimizes power and clock. TSMC, on the other hand, believes that its N3P (3-nanometer) technology will rival Intel’s 18A in power consumption, performance, and area (PPA), while its N2 (2-nanometer) will surpass it in all aspects.

Additionally, Intel’s 20A manufacturing technology is reportedly scheduled for launch in 2024, introducing two technologies: RibbonFET surround gate transistors and backside power delivery network (BSPDN). These aim to achieve higher performance, lower power consumption, and increased transistor density.

Meanwhile, Intel’s 18A production node aims to further refine the innovations of 20A and provide additional PPA improvements from late 2024 to early 2025. Per Intel’s statements regarding its fab processes, its 2-nanometer technology is expected to be the earliest to debut.

Of particular note, Intel announced for the first time at the conference the development of 14A (1.4nm) and its evolutionary version, 14A-E. Intel’s 14A process is the industry’s first node to utilize ASML High-NA EUV lithography tools, making Intel the first company in the industry to acquire cutting-edge High-NA tools. Intel expects to develop 14A by 2027.

• Rapidus

In addition to the aforementioned semiconductor foundries, a Japanese company, Rapidus, is worth noting as well. Established in August 2022, Rapidus was jointly founded by eight Japanese companies including Toyota, Sony, NTT, NEC, SoftBank, Denso, NAND Flash giant Kioxia, and Mitsubishi UFJ.

On January 22nd of 2024, Rapidus President Junichi Koike announced during a press conference that construction of the Rapidus 2-nanometer chip fab in Japan is progressing smoothly, and the trial production line is scheduled to commence operations in April 2025 as planned. Additionally, there are plans for the construction of a second and third facility in the future.

In September of last year, Rapidus began construction of Japan’s first logic chip fab, “IIM-1,” in Chitose City, Hokkaido, capable of producing chips below 2 nanometers. It is reported that the fab is expected to be completed by December of this year.

Previously, Rapidus signed a collaboration agreement with IBM to develop technology based on IBM’s 2-nanometer process. IBM had already introduced the world’s first 2-nanometer process chip back in 2021. Similarly, IBM’s 2-nanometer process also utilizes GAA (Gate-All-Around) structure. This partnership provides Rapidus with the technical support necessary for advanced process development.

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• [News]The 2nm Semiconductor Foundry Race Between TSMC, Samsung, Rapidus Begins with an Equipment Battle

(Photo credit: TSMC)

As Samsung’s foundry business closely trails TSMC, Economic Daily News has reported that Samsung is poised to secure orders for Meta’s next-gen AI chips, manufactured on a 2-nanometer process. If so, this may mark Samsung’s first 2nm customer, intensifying the rivalry with TSMC in the 2nm race.

According to The Korea Times, the potential collaboration between Meta and Samsung was discussed during Meta CEO Zuckerberg’s recent visit to South Korea.

The report cites anonymous officials stating that during Zuckerberg’s meeting with South Korean President Yoon Suk Yeol, he disclosed Meta’s reliance on TSMC. However, the current situation is described as “volatile” due to TSMC’s tight production capacity, which could potentially affect Meta’s supply in the long run.

Nevertheless, neither Meta nor South Korean officials have confirmed these rumors.

Currently, Meta has entrusted TSMC with the production of two AI chips. As per the Economic Daily News citing sources, the biggest challenge for Samsung’s foundry business lies in yield rates.

Previously, poor yield rates prompted Apple, Qualcomm, and Google to switch their orders to TSMC. If Meta indeed turns to Samsung for the next-generation AI chips, the key to the success of their collaboration still lies in yield rates.

As per Samsung’s previous roadmap, the 2-nanometer SF2 process is set to debut in 2025. Compared to the second-generation 3GAP process at 3 nanometers, it offers a 25% improvement in power efficiency at the same frequency and complexity, as well as a 12% performance boost at the same power consumption and complexity, while reducing chip area by 5%.

As stated in Samsung’s Foundry Forum (SFF) plan, Samsung will begin mass production of the 2nm process (SF2) in 2025 for mobile applications, expand to high-performance computing (HPC) applications in 2026, and further extend to the automotive sector and the expected 1.4nm process by 2027.

Read more

• [News] Samsung Secures 2-Nanometer Order from Japanese AI Startup Preferred Networks
• [News] Samsung’s Discount Strategy Challenges TSMC as the Battle for 2nm Orders Heats Up

(Photo credit: Samsung)

Intel, according to South Korea’s media outlet TheElec, is actively promoting its 18A process (equivalent to 1.8 nanometers) to South Korean fabless chip companies.

The report cites industry sources revealing that Intel CEO Pat Gelsinger personally engaged with senior executives of these South Korean fabless IC design companies last year. He briefed them on the latest developments in Intel’s foundry plans.

The same source further indicates that Intel is vigorously marketing the 18A process to South Korean chip startups and pledges various benefits to them.

Last week, Intel unveiled its 14A process, equivalent to a 1.4-nanometer process, and announced that chips utilizing this process will enter mass production in 2027. Intel has also announced that it has secured USD 15 billion in orders during its event Intel Foundry Direct Connect at San Jose.

Intel continues to emphasize its goal of becoming the second-largest foundry by 2030, aiming to surpass current foundry runner-up Samsung Electronics and trailing behind market leader TSMC.

As for the mass production of the 18A process, Intel has indicated that it is scheduled to commence by the end of this year. This signifies that Intel’s process technology will surpass both Samsung and TSMC, as the latter two are currently preparing to launch 2-nanometer processes.

Samsung is planning to utilize the gate-all-around (GAA) transistor architecture, initially developed for the 3-nanometer process, for its upcoming 2-nanometer process. On the other hand, TSMC and Intel have opted to employ the fin field-effect transistor (FinFET) structure for their 3-nanometer chips.

Currently, these three major players are actively vying for customers. A report from the Business Korea has indicated that Samsung Electronics recently secured an order from the Japanese AI startup Preferred Networks (PFN) to produce semiconductors based on the 2-nanometer process.

Per the report, while this Japanese company initially planned to use TSMC’s process for producing their Gen 2 AI chips, they will now transition to Samsung’s 2-nanometer process.

Read more

• [News] Gelsinger Opens Up, as Intel Reportedly Expands Orders to TSMC
• [News] Samsung Secures 2-Nanometer Order from Japanese AI Startup Preferred Networks

(Photo credit: Intel)

Currently, the top three leaders—Samsung, SK Hynix, and Micron—in the HBM sector are undergoing unprecedented expansion. Below is an overview of the progress made by each of these giants in the realm of HBM:

• Samsung: HBM Production to Increase 2.5 Times in 2024, Another 2 Times in 2025

Samsung Electronics has begun expanding its HBM3 supply since the fourth quarter of 2023. Prior to this, internal messages within Samsung during the fourth quarter of 2023 indicated that samples of the next-generation HBM3e with an 8-layer stack had been provided to customers, with plans for mass production to commence in the first half of this year.

Han Jin-man, Executive Vice President in charge of Samsung’s semiconductor business in the United States, stated at CES 2024 this year that Samsung’s HBM chip production volume will increase 2.5 times compared to last year and is projected to double again next year.

Samsung officials also revealed that the company plans to increase the maximum production of HBM to 150,000 to 170,000 units per month before the fourth quarter of this year in a bid to compete for the HBM market in 2024.

Previously, Samsung Electronics spent KRW 10.5 billion to acquire the plant and equipment of Samsung Display located in Tianan City, South Korea, to expand HBM capacity. They also plan to invest KRW 700 billion to 1 trillion in building new packaging lines.

• SK Hynix: To Commence Mass Production of World’s First Fifth-Generation High-Bandwidth Memory HBM3e in March

According to the latest report from Korean media Moneytoday on February 20th, SK Hynix will commence mass production of the world’s first fifth-generation high-bandwidth memory, HBM3e, in March this year. The company plans to supply the first batch of products to NVIDIA within the next month.

However, SK hynix noted that it “cannot confirm any details related to its partner.”

In its financial report, SK Hynix indicated plans to increase capital expenditure in 2024, with a focus on high-end storage products such as HBM. The HBM production capacity is expected to more than double compared to last year.

Previously, SK Hynix forecasted that by 2030, its HBM shipments would reach 100 million units annually. As a result, the company has decided to allocate approximately KRW 10 trillion (approximately USD 7.6 billion) in CAPEX for 2024. This represents a significant increase compared to the projected CAPEX of KRW 6 to 7 trillion in 2023, with an increase ranging from 43% to 67%.

The focus of the expansion is on constructing and expanding factories. In June of last year, Korean media reported that SK Hynix was preparing to invest in backend process equipment to expand its HBM3 packaging capabilities at its Icheon plant. By the end of this year, it is expected that the scale of backend process equipment at this plant will nearly double.

Furthermore, SK Hynix is also set to construct a state-of-the-art manufacturing facility in Indiana, USA. According to the Financial Times, this South Korean chip manufacturer will produce HBM stacks at this facility, which will be used for NVIDIA GPUs produced by TSMC.

• Micron: Continuing the Pursuit, Betting on HBM4

Micron holds a relatively low share in the global HBM market. In order to narrow this gap, Micron has placed a significant bet on its next-generation product, HBM3e.

Sanjay Mehrotra, CEO of Micron, stated, ” Micron is in the final stages of qualifying our industry-leading HBM3e to be used in NVIDIA’s next-generation Grace Hopper GH200 and H200 platforms.”

Micron plans to begin mass shipments of HBM3e memory in early 2024. Mehrotra emphasized that their new product has garnered significant interest across the industry, implying that NVIDIA may not be the sole customer ultimately utilizing Micron’s HBM3e.

In this competition where there is no first-mover advantage, Micron seems to be betting on the yet-to-be-determined standard of the next-generation HBM4. Official announcements reveal that Micron has disclosed its next-generation HBM memory, tentatively named HBM Next. It is expected that HBM Next will offer capacities of 36GB and 64GB, available in various configurations.

Unlike Samsung and SK Hynix, Micron does not intend to integrate HBM and logic chips into a single chip. In the development of the next-generation HBM, the Korean and American memory manufacturers have distinct strategies.

Micron may address AMD, Intel, and NVIDIA that faster memory access speeds can be achieved through combination chips like HBM-GPU. However, relying solely on a single chip means greater risk.

As per TrendForce, HBM4 is planned to be launched in 2026. It is expected that specifications and performance, including those for NVIDIA and other CSP (Cloud Service Providers) in future product applications, will be further optimized.

With specifications evolving towards higher speeds, it will be the first time that the base die of HBM, also known as the Logic die, will adopt a 12nm process wafer. This part will be provided by foundries, necessitating collaboration between foundries and memory manufacturers for single HBM product integration.

Furthermore, as customer demands for computational efficiency increase, HBM4 is expected to evolve beyond the existing 12hi (12-layer) stack to 16hi (16-layer) configurations. The anticipation of higher layer counts is also expected to drive demand for new stacking methods such as hybrid bonding. HBM4 12hi products are slated for release in 2026, while 16hi products are expected to debut in 2027.

Read more

• [News] SK Hynix Signs Prioritized Supply Agreement with NVIDIA for HBM3e, 2023 Q4 Revenue Expected to Surpass KRW 10 Trillion Again
• [News] H200 Unveiled: NVIDIA Integrates HBM3e for Enhanced AI Performance

(Photo credit: Samsung)