Currently, the top three leaders—Samsung, SK Hynix, and Micron—in the HBM sector are undergoing unprecedented expansion. Below is an overview of the progress made by each of these giants in the realm of HBM:

• Samsung: HBM Production to Increase 2.5 Times in 2024, Another 2 Times in 2025

Samsung Electronics has begun expanding its HBM3 supply since the fourth quarter of 2023. Prior to this, internal messages within Samsung during the fourth quarter of 2023 indicated that samples of the next-generation HBM3e with an 8-layer stack had been provided to customers, with plans for mass production to commence in the first half of this year.

Han Jin-man, Executive Vice President in charge of Samsung’s semiconductor business in the United States, stated at CES 2024 this year that Samsung’s HBM chip production volume will increase 2.5 times compared to last year and is projected to double again next year.

Samsung officials also revealed that the company plans to increase the maximum production of HBM to 150,000 to 170,000 units per month before the fourth quarter of this year in a bid to compete for the HBM market in 2024.

Previously, Samsung Electronics spent KRW 10.5 billion to acquire the plant and equipment of Samsung Display located in Tianan City, South Korea, to expand HBM capacity. They also plan to invest KRW 700 billion to 1 trillion in building new packaging lines.

• SK Hynix: To Commence Mass Production of World’s First Fifth-Generation High-Bandwidth Memory HBM3e in March

According to the latest report from Korean media Moneytoday on February 20th, SK Hynix will commence mass production of the world’s first fifth-generation high-bandwidth memory, HBM3e, in March this year. The company plans to supply the first batch of products to NVIDIA within the next month.

However, SK hynix noted that it “cannot confirm any details related to its partner.”

In its financial report, SK Hynix indicated plans to increase capital expenditure in 2024, with a focus on high-end storage products such as HBM. The HBM production capacity is expected to more than double compared to last year.

Previously, SK Hynix forecasted that by 2030, its HBM shipments would reach 100 million units annually. As a result, the company has decided to allocate approximately KRW 10 trillion (approximately USD 7.6 billion) in CAPEX for 2024. This represents a significant increase compared to the projected CAPEX of KRW 6 to 7 trillion in 2023, with an increase ranging from 43% to 67%.

The focus of the expansion is on constructing and expanding factories. In June of last year, Korean media reported that SK Hynix was preparing to invest in backend process equipment to expand its HBM3 packaging capabilities at its Icheon plant. By the end of this year, it is expected that the scale of backend process equipment at this plant will nearly double.

Furthermore, SK Hynix is also set to construct a state-of-the-art manufacturing facility in Indiana, USA. According to the Financial Times, this South Korean chip manufacturer will produce HBM stacks at this facility, which will be used for NVIDIA GPUs produced by TSMC.

• Micron: Continuing the Pursuit, Betting on HBM4

Micron holds a relatively low share in the global HBM market. In order to narrow this gap, Micron has placed a significant bet on its next-generation product, HBM3e.

Sanjay Mehrotra, CEO of Micron, stated, ” Micron is in the final stages of qualifying our industry-leading HBM3e to be used in NVIDIA’s next-generation Grace Hopper GH200 and H200 platforms.”

Micron plans to begin mass shipments of HBM3e memory in early 2024. Mehrotra emphasized that their new product has garnered significant interest across the industry, implying that NVIDIA may not be the sole customer ultimately utilizing Micron’s HBM3e.

In this competition where there is no first-mover advantage, Micron seems to be betting on the yet-to-be-determined standard of the next-generation HBM4. Official announcements reveal that Micron has disclosed its next-generation HBM memory, tentatively named HBM Next. It is expected that HBM Next will offer capacities of 36GB and 64GB, available in various configurations.

Unlike Samsung and SK Hynix, Micron does not intend to integrate HBM and logic chips into a single chip. In the development of the next-generation HBM, the Korean and American memory manufacturers have distinct strategies.

Micron may address AMD, Intel, and NVIDIA that faster memory access speeds can be achieved through combination chips like HBM-GPU. However, relying solely on a single chip means greater risk.

As per TrendForce, HBM4 is planned to be launched in 2026. It is expected that specifications and performance, including those for NVIDIA and other CSP (Cloud Service Providers) in future product applications, will be further optimized.

With specifications evolving towards higher speeds, it will be the first time that the base die of HBM, also known as the Logic die, will adopt a 12nm process wafer. This part will be provided by foundries, necessitating collaboration between foundries and memory manufacturers for single HBM product integration.

Furthermore, as customer demands for computational efficiency increase, HBM4 is expected to evolve beyond the existing 12hi (12-layer) stack to 16hi (16-layer) configurations. The anticipation of higher layer counts is also expected to drive demand for new stacking methods such as hybrid bonding. HBM4 12hi products are slated for release in 2026, while 16hi products are expected to debut in 2027.

Read more

• [News] SK Hynix Signs Prioritized Supply Agreement with NVIDIA for HBM3e, 2023 Q4 Revenue Expected to Surpass KRW 10 Trillion Again
• [News] H200 Unveiled: NVIDIA Integrates HBM3e for Enhanced AI Performance

(Photo credit: Samsung)

Despite challenges, Samsung Semiconductor remains optimistic about the market outlook for the second half of the year. According to a report from TechNews citing sources , to compete with TSMC and enhance efficiency to meet market demands, Samsung is reportedly adjusting the expansion schedule of its fabs.

As per a report from global media outlet SamMobile, Samsung Semiconductor is adjusting the construction schedule of its Pyeongtaek Plant 4 (P4) in South Korea to prioritize the construction of the PH2 production line, temporarily halting the construction of the new production line at the semiconductor plant 5 (P5).

In addition, Samsung is said to be reallocating resources to invest in the PH2 production line at the P4 plant. Once the cleanroom is completed, it will be dedicated to contract chip manufacturing.

Pyeongtaek is a major semiconductor manufacturing center for Samsung, serving as a significant hub for its foundry business and a crucial memory plant. South Korea’s Pyeongtaek currently has the operational P1, P2, and P3 plants, with the construction of the P4 and P5 underway.

Reportedly, Samsung is expected to expand its contract manufacturing capacity to secure more clients from its competitor, TSMC. Additionally, the P4 plant will also establish the PH3 production line to produce DRAM and other components. Samsung’s adjustment in plans reflects its anticipation of rising market demand and its efforts to prepare to meet those demands.

While Samsung stated that the suspension of the P5 plant was for inspection purposes, sources cited in the SamMobile report believe that Samsung likely slowed down the progress of the P5 plant due to the previous downturn in the semiconductor market.

Read more

• [News] Samsung Secures 2-Nanometer Order from Japanese AI Startup Preferred Networks
• [News] Samsung’s Discount Strategy Challenges TSMC as the Battle for 2nm Orders Heats Up

(Photo credit: Samsung)

TSMC is scheduled to hold the opening ceremony for its Kumamoto plant on February 24. In contrast, the construction progress of its Arizona plant in the United States has been relatively slow.

According to TechNews citing a research report from the Center for Security and Emerging Technology (CSET), the construction speed of semiconductor plants in the United States is the slowest globally due to the intricate regulatory environment. While the U.S. chip law supports the semiconductor industry, it is insufficient to address construction costs and timelines.

Looking at the construction speed of the three major foundries in the United States, they have indeed all fallen behind their original targets. For instance, TSMC’s Arizona plant was delayed by a year, Intel’s Ohio plant was pushed from 2025 to the end of 2026, and Samsung’s Texas plant, due to not receiving chip bill subsidies, was also delayed to 2025.

As per research conducted by CSET on the construction of 635 semiconductor plants from 1990 to 2020, the average time from groundbreaking to production was 682 days globally. However, in the United States, the average was 736 days, significantly higher than the global average and second only to Southeast Asia’s 781 days.

In comparison, the construction speeds in Taiwan, South Korea, and Japan are 654 days, 620 days, and 584 days, respectively, with Japan’s performance being quite remarkable. As for Europe and the Middle East, the average is 690 days, while in China, it is 701 days.

The report further indicates that in the 1990s and 2000s, foundries in the United States had a relatively faster construction speed, with an average time of about 675 days. However, by the 2010s, this time frame extended to 918 days.

Meanwhile, during the same period, the construction speed in China and Taiwan significantly accelerated, with average completion times of 675 days and 642 days, respectively.

Furthermore, the number of foundries in the United States has been declining, from 55 in the 1990s to 43 in the 2000s and 22 in the 2010s. In contrast, the construction speed of foundries in China has significantly accelerated, from 14 in the 1990s to 75 in the 2000s, and further to 95 in the 2010s.

Although China’s semiconductor technology is still in the catch-up phase, the construction of foundries positions it as a dominant force in the industry.

Stringent Regulations in the United States Lead to Slow Factory Construction Despite Favorable Conditions 

The report highlights seven key requirements for foundry construction: Large plots of land, low seismic activity, stable water supply, stable supply of electricity, talent, transportation infrastructure, and nearby land for co-location with key suppliers.

In these aspects, the United States outperforms Taiwan; however, the primary obstacle is regulatory issues.

Due to the unique federal structure of the United States, foundry construction must comply with federal, state, and local regulations, resulting in an exceptionally complex regulatory process. Additionally, environmental policies pose obstacles to foundry construction, particularly due to stringent requirements for environmental protection

The report suggests that to enhance the United States’ competitiveness in the global semiconductor industry, the government needs to streamline regulatory processes, eliminate redundant regulations, and establish expedited pathways to accelerate semiconductor industry construction projects.

Additionally, there should be an acceleration of environmental review processes and investment in the development of alternative materials to ensure sustainable semiconductor material supplies.

With the continued growth in global semiconductor demand, the construction speed and efficiency of US semiconductor fabs will directly impact its position in the global market.

To maintain its leading position, per the report, the United States urgently needs to take action to address this issue. Currently, it is unclear how much impact the delayed construction of semiconductor fabs by TSMC, Intel, and Samsung will have.

Read more

• [News] High Efficiency in TSMC Kumamoto Plant Construction Sets Stage for Potential Advanced Packaging Investment in Japan
• [News] TSMC Reportedly Announcing Kumamoto Plant 2 in Japan, while U.S. Subsidies Expected by End of March

(Photo credit: TSMC)

It was reported earlier that during Samsung Electronics’ fourth-quarter financial announcement in 2023, the company revealed that its foundry division had secured orders for 2-nanometer AI chips. However, at the time, Samsung did not disclose the name of the relevant customer. Now, according to a report from the Business Korea, the customer is the Japanese AI startup Preferred Networks.

The report indicates that Preferred Networks, which placed an order with Samsung’s foundry division for 2-nanometer AI chips, was founded in 2014 and is in the field of AI deep learning development.

The company has attracted significant investments from major Japanese industrial enterprises such as Toyota, NTT, and Fanuc. The order placed with Samsung’s foundry division for 2-nanometer AI chips also includes HBM and advanced packaging.

As per Samsung’s previous roadmap, the 2-nanometer SF2 process is set to debut in 2025. Compared to the second-generation 3GAP process at 3 nanometers, it offers a 25% improvement in power efficiency at the same frequency and complexity, as well as a 12% performance boost at the same power consumption and complexity, while reducing chip area by 5%.

As stated in Samsung’s Foundry Forum (SFF) plan, Samsung will begin mass production of the 2nm process (SF2) in 2025 for mobile applications, expand to high-performance computing (HPC) applications in 2026, and further extend to the automotive sector and the expected 1.4nm process by 2027.

According to previous reports, the leading foundry TSMC has already disclosed the test results of its 2-nanometer prototype process to major clients such as Apple and NVIDIA, with the goal of commencing mass production by 2025. Apple is set to become TSMC’s inaugural customer for the 2-nanometer process, positioning TSMC at the forefront of competition in the 2-nanometer advanced process technology.

However, according to a previous report from the Financial Times, Samsung is preparing to attract customers to place orders for its 2-nanometer process at lower prices. The move is expected to compete for a portion of Qualcomm’s flagship chip production, as Qualcomm, a major customer of TSMC, may consider shifting some of its flagship chip production to Samsung’s 2-nanometer process.

Read more

• [News] Samsung’s Discount Strategy Challenges TSMC as the Battle for 2nm Orders Heats Up
• [News] Intense Competition in Advancing Processes at the 2nm by Samsung, Intel, and TSMC

(Photo credit: Samsung)

Samsung’s flagship mobile processor, the Exynos 2400, produced using the 4LPP+ process technology, currently boasts a yield rate of approximately 60%, as per sources cited by TechNews. While this figure falls short of competitors, notably TSMC’s N4P process technology with yields surpassing 70%, it represents a significant improvement from Samsung’s own 25% yield rate over a year ago.

Samsung’s Exynos 2400 flagship mobile processor is the company’s first to utilize Fan-Out Wafer-Level Packaging (FOWLP). Samsung claims that FOWLP technology enhances heat resistance by 23% and boosts multicore performance by 8%. Consequently, the Exynos 2400 mobile processor delivers commendable performance in the latest 3DMark Wild Life benchmark tests.

In fact, Samsung previously announced plans to commence mass production of the SF3 chip in the second half of 2024, followed by the introduction of its 2-nanometer process technology between 2025 and 2026.

Industry sources cited in the report also indicate that Samsung’s foundry business has begun trial production for its second-generation 3-nanometer process technology, SF3. Furthermore, the company aims to increase its yield rate to over 60% within the next six months.

It is noteworthy that Samsung’s 3nm technology is highly aggressive compared to TSMC’s approach, which will transition to GAA transistors with its 2nm process. Samsung’s first-generation 3nm process already incorporates GAA transistor technology, specifically the MBCFET (Multi-Bridge Channel Field-Effect Transistor), known as SF3E, or 3GAE technology.

As per WeChat account ic211ic cited sources in the report, Samsung’s 3nm GAA technology utilizes wider nanosheets compared to the narrow nanowire GAA technology, offering higher performance and energy efficiency. With the 3nm GAA technology, Samsung can adjust the channel width of nanosheet transistors to optimize power consumption and performance, meeting diverse customer requirements.

Additionally, the flexibility of GAA design is highly advantageous for Design-Technology Co-Optimization (DTCO), contributing to achieving better Power, Performance, and Area (PPA) advantages.

In comparison to Samsung’s 5nm process, the first-generation 3nm process reduces power consumption by 45%, enhances performance by 23%, and decreases chip area by 16%. The upcoming second-generation 3nm process is expected to further reduce power consumption by 50%, boost performance by 30%, and reduce chip area by 35%.

(Photo credit: Samsung)