South Korean President Yoon Suk Yeol concluded his visit to the Netherlands, announcing the establishment of a “Semiconductor Alliance” between South Korea and the Netherlands. The alliance involves collaboration between Dutch semiconductor equipment giant ASML and South Korean companies Samsung and SK Hynix. This marks South Korea’s first alliance announcement with a specific country.

According to the Korea Times and South Korean President Office’s press release on December 13th, President Yoon Suk Yeol’s held a dialogue with Dutch Prime Minister Mark Rutte during the state visit to the Netherlands. They issued a joint statement formalizing the “Semiconductor Alliance” and establishing bilateral mechanisms for economic, security, and industrial consultations.

On December 12th, President Yoon Suk Yeol led a delegation to ASML’s headquarters in the Netherlands, including representatives from South Korean semiconductor giants Samsung and SK Hynix, as reported by the Korea Times. During the visit, Samsung and ASML signed an MOU, jointly investing approximately KRW 1 trillion (about USD 7.6 billion) to establish a research fab in South Korea.

Bloomberg also reports that the new fab will expand ASML’s market in South Korea, where it already operates four fabs, servicing clients including Samsung. ASML’s exclusive EUV technology is crucial amid the US-China tech trade tensions, making regional diversification increasingly important for the company.

ASML is a leading global player of semiconductor EUV lithography systems, which is crucial for processing semiconductor manufacturing’s most vital steps. EUV equipment are a pivotal part of chip manufacturing, and ASML can produce only around 60 EUV devices annually. Currently, 70% of ASML’s EUV equipment are purchased by market leader TSMC.

Previous reports from South Korean media highlighted Samsung’s substantial EUV equipment purchases from ASML, totaling 50 units. Samsung is the world’s first company to produce 3nm chips, commencing production of the first-generation 3nm chips in the latter half of 2022. It aims to start mass production of the second-generation 3nm chips in the first half of the next year and targets producing 2nm chips by 2025 and 1.4nm chips by 2027.

(Image: 대한민국 대통령실)

Rumors suggest TSMC will set up a new fab that deploys 2nm and more advances processes in the Central Taiwan Science Park (CTSP) Phase 2, Taichung City, Taiwan. The city mayor Shiow-Yen Lu has confirmed TSMC’s entry into Phase 2, designating all allocated land exclusively for TSMC 2nd Fab in CTSP. According to the local government, the new fab is expected to house “processes advances than 2nm,” expressing the hope that TSMC will bring its latest technology to Taichung City.

The latest news about TSMC’s new plant has emerged. CNA reported that during the regular session of the Taichung City Council on December 12th, the mayor responded to councilors regarding the progress of Taichung’s efforts to attract TSMC’s new plant. Mayor stated that the city government has secured the deal, confirming that TSMC will establish itself in the CTSP Phase 2.

Mayor Lu explained that due to the immense scale of TSMC’s Taichung 2nd Fab, the Ministry of Economic Affairs in Taiwan is assisting as well. While CTSP Phase 1 accommodates numerous companies, almost all the land in Phase 2 is allocated for TSMC’s Taichung 2nd Fab.

In response, TSMC expressed gratitude for the support from the Taichung city government and pledged to continue cooperating with the relevant procedures. Regarding whether Phase 2 of CTSP will adopt technology for 2nm and more advances process, TSMC did not provide further clarification.

TSMC has also responded to earlier reports about Samsung offering discounts so as to be more effective in competing with TSMC for 2nm orders. During a joint interview before the Taiwan Executive Yuan’s Science & Technology Meeting on December 13th, TSMC Chairman Mark Liu stated that TSMC’s customers prioritize technological quality. As for the outlook for the coming year, Liu expressed hope for a very healthy year.

▲ TSMC’s Current Layout of Global Production Capacity
Edited by TrendForce, November, 2023

(Image: TSMC)

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According to icsmart’s report, in October, Samsung Electronics and SK Hynix received an indefinite exemption from the U.S. government’s control over exports to China, allowing them to import semiconductor manufacturing equipment without special permission for their facilities. Samsung has initiated efforts to boost capacity at its Xi’an plant.

Reportedly, Samsung Electronics‘s 12-inch NAND flash M-FAB fab has officially entered the main construction phase.

Established in Xi’an in 2012, it is Samsung’s sole overseas memory production base and has evolved into the world’s largest NAND Flash manufacturing facility. The fab produces over 265,000 12-inch wafers per month, contributing to over 40% of Samsung’s total NAND Flash flash production.

According to publicly available data, the initial investment for the first phase of Samsung’s Xi’an fab in China was USD 10.87 billion, and it commenced production in May 2014, primarily manufacturing 3D NAND flash memory chips.

On August 30, 2017, Samsung Semiconductor announced a USD 7 billion investment to build the second phase of the 12-inch NAND flash project, establishing a new NAND flash production line. In December 2019, the company decided to further invest USD 8 billion to expand the scale of the second-phase project.

Business Korea reports that Samsung executives have decided to upgrade the Xi’an NAND Flash fab to a 236-layer stacking process and significantly expand production. Industry sources indicate that Samsung has initiated the procurement of semiconductor equipment, with deliveries scheduled for the end of the year.

In 2024, the company plans to introduce eighth-generation NAND Flash equipment in succession. This move is seen by the industry as a strategy to counter the soft demand in the global NAND Flash market.

(Photo credit: Samsung)

Both TSMC and Samsung plan to start production on the 2nm process in 2025, triggering an early battle for related orders. According to sources reported by the Financial Times (FT), Qualcomm intends to shift production of its next-generation high-end mobile chips from TSMC to Samsung’s 2nm process. Samsung, offering substantial discounts, is aggressively pursuing orders from major players like NVIDIA, posing a challenge to TSMC’s dominance.

According to reports citing insider information, TSMC has showcased its 2nm prototype test results to major clients like Apple and NVIDIA. Additionally, sources indicate that Samsung is not only planning to introduce its 2nm prototype but is also offering discounted prices, attracting interest from prominent clients, including NVIDIA.

The report highlights that Qualcomm is planning to use Samsung’s “SF2” (2nm) process for the next generation of high-end smartphone chips. Samsung, as the first company to globally mass-produce 3nm (SF3) chips last year, is also the pioneer in adopting the new Gate-All-Around (GAA) transistor architecture.

Samsung indicated that, “We have fully deployed and can mass-produce SF2 in 2025. Since we are the first company to enter and transform the GAA architecture, we hope that the progress from SF3 to SF2 will be relatively smooth.”

However, insiders have disclosed that Samsung’s yield for the most basic 3nm chips is only 60%, significantly below customer expectations. Moreover, when producing chips with complexity equivalent to Apple’s A17 Pro or NVIDIA graphics processing units (GPUs), the yield may further decrease.

Global giants such as Qualcomm and NVIDIA follow a diversified wafer foundry strategy, but they still rely heavily on TSMC for now. Previously, NVIDIA’s Chief Financial Officer, Colette Kress, hinted during the UBS Global Technology Conference that NVIDIA may consider Intel for the production of its next-generation chips, potentially breaking away from the exclusive partnership with TSMC for AI chips.

Now, Qualcomm is also exploring collaboration with Samsung for the 2nm process, intensifying the pressure on TSMC to address potential order losses from two major clients in advanced semiconductor manufacturing.

TSMC, on the other hand, informed the Financial Times that the development progress of its 2nm process is proceeding smoothly, and it is scheduled for production in 2025. When launched, it will represent the industry’s most advanced semiconductor technology in terms of density and energy efficiency.

In a previous investor conference, TSMC stated that there is significant customer interest and engagement in 2nm for high-speed computing and smartphone applications. It is expected that 2nm, when introduced in 2025, will be the most advanced semiconductor technology in the industry, comparable or even superior to 3nm at the same stage.

TSMC plans to launch the 2nm backside power rail solution in the second half of 2025, with mass production scheduled for 2026.

Besides TSMC and Samsung actively advancing towards 2nm and more advanced processes, Intel has also joined the competition. The Financial Times characterizes this race for the 2nm process as “shaping the future of a USD 500 billion industry.”

Intel is progressing along its previously set 5 process nodes in a four-year trajectory. The Intel 4 process is ready for mass production, and the Intel 3 process is planned for launch later this year. Intel CEO, Pat Gelsinger, has previously showcased the Intel 20A wafer, which is expected to enter the pre-production phase in the first half of next year. The Intel 18A process is scheduled for mass production in the second half of 2024.

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(Photo credit: Samsung)

The shortage of advanced packaging production capacity is anticipated to end earlier than expected. Industry suggests that Samsung’s inclusion in providing HBM3 production capacity has led to an increased supply of memory essential for advanced packaging. Coupled with TSMC’s strategy of enhancing advanced packaging production capacity through equipment modifications and partial outsourcing, and the adjustments made by some CSP in designs and placing orders, the bottleneck in advanced packaging capacity is poised to open up as early as the first quarter of the upcoming year, surpassing industry predictions by one quarter to half a year, according to the UDN News.

TSMC refrains from commenting on market speculations, while Samsung has already issued a press release signaling the expansion of HBM3 product sales to meet the growing demand for the new interface, concurrently boosting the share of advanced processes.

Industry indicates that the previous global shortage of AI chips primarily resulted from inadequate advanced packaging capacity. Now the shortage in advanced packaging capacity is expected to end sooner, it implies a positive shift in the supply of AI chips.

Samsung, alongside Micron and SK Hynix, is a key partner for TSMC in advanced packaging. In a recent press release, Samsung underscores its close collaboration with TSMC in previous generations and the current high-bandwidth memory (HBM) technology, supporting the compatibility of the CoWoS process and the interconnectivity of HBM. Having joined the TSMC OIP 3DFabric Alliance in 2022, Samsung is set to broaden its scope of work and provide solutions for future generations of HBM.

Previously, the industry points out that the earlier shortage of AI chips stemmed from three main factors: insufficient advanced packaging capacity, tight HBM3 memory capacity, and some CSPs repeatedly placing orders. Now, the obstacles related to these factors are gradually being overcome. In addition to TSMC and Samsung’s commitment to increasing advanced packaging capacity, CSPs are adjusting designs, reducing the usage of advanced packaging, and canceling previous repeated orders – all of which are the key factors.

TSMC’s ongoing collaboration with OSATs(Outsourced Semiconductor Assembly And Test) to expedite WoS capacity expansion is gaining momentum. NVIDIA confirmed during a recent financial calls that it has certified other CoWoS advanced packaging suppliers’ capacity as a backup. Industry speculation suggests that certifying the capacity of other CoWoS suppliers for both part of the front-end and back-end production will contribute to TSMC and its partners achieving the target of reaching a monthly CoWoS capacity of approximately 40,000 pieces in the first quarter of the next year.

Furthermore, previous challenges in expanding advanced packaging production capacity, especially in obtaining overseas equipment, are gradually being overcome. With equipment optimization, more capacity is being extracted, alleviating the shortage of AI chip capacity.

(Image: Samsung)

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