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After reporting disappointing third-quarter earnings forecast earlier this week, Samsung’s head of Device Solutions (DS) division, Jun Young-hyun, had issued an unusual apology. Now the struggling giant seems to be making its next move. According to the latest report by the Korea Economic Daily, the company is set to significantly reduce its chip executive positions and reorganize its semiconductor-related operations.
The report notes that Samsung is currently auditing the memory department within the DS division, which manages its semiconductor business. It is worth noting that the review is said to be led by Vice Chairman Jun Young-hyun himself, while the audit may result in substantial job cuts at the executive level.
According to insiders cited by the report, a major executive reshuffle is planned as part of the company’s year-end personnel changes.
For more details, the report indicates that in the year-end reshuffle, Samsung is expected to overhaul the leadership of its three core business units within the DS division, which encompasses memory, foundry, and System LSI. Moreover, key positions, such as the chief technology officer and heads of manufacturing and technology, are also subject to change, according to sources cited by the report.
According to the information cited by the report, as of the second quarter, Samsung’s DS division had 438 executives, making up 38% of the company’s total 1,164 executives. Notably, this number is more than double that of the current HBM leader, SK hynix, which has 199 executives.
According to sources cited by Business Korea, Samsung is also expected to simplify its foundry operations and restructure the Semiconductor Research Center, which is responsible for developing future chip technologies.
Although Samsung did not provide a detailed performance breakdown by division, analysts cited by the report estimate that its foundry business likely suffered losses of approximately 1.5 trillion won in the third quarter. On the other hand, its core memory business would likely to generate an operating profit of 5.5 trillion won, which marks the first time the company’s memory profit falls short of SK hynix’s, the report suggests.
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(Photo credit: Samsung)
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Rumors suggest that Samsung’s upcoming Galaxy S25 models will adopt a dual-chipset strategy by adopting MediaTek’s Dimensity 9400. This approach is intended to lessen the company’s dependence on Qualcomm and to reduce its chipset costs, according to a report from Wccftech.
While neither Samsung nor MediaTek have confirmed this information, it may have been inadvertently revealed by Google in its blog post, Wccftech notes. In a blog article released by Google DeepMind at the end of September, the progress of AlphaChip, which is the AI division of Google, was discussed, emphasizing how it accelerates and optimizes chip design.
Notably, the article suggests the potential collaboration between Samsung and MediaTek, according to Wccftech.
Although the article does not explicitly mention MediaTek’s Dimensity 9400 or the Galaxy S25 series, it does mention the Dimensity Flagship 5G. This could imply the Dimensity 9400 and the Galaxy S25 series, since the Galaxy S24 series does not currently feature any high-end MediaTek chipsets.
As per a report from TechNews, the Dimensity 9400 has been officially launched today (October 9th), while the Galaxy S25 series is expected to be unveiled early next year, aligning with the details mentioned in the blog article released by Google DeepMind.
It is worth noting that Samsung is initially expected to integrate some of the new Galaxy S25 models with its own Exynos 2500. However, according to Wccftech, due to the unstable yield rates of the 3 nm GAA process, Samsung not only struggled to attract potential consumers but also faced the possibility of delaying the launch schedule for its new flagship chipset.
Nevertheless, as suggested by Wccftech, the Exynos 2500 might not be abandoned. Rumors indicate that it might be used in its ‘price to performance’ Galaxy S25 FE, along with its future foldable smartphones.
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(Photo credit: Samsung)
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There are signs that OpenAI, the company that rose to fame with its AI models, is now eyeing the semiconductor manufacturing sector. However, can building a wafer fab be an easy success?
Recently, international media revealed details of OpenAI CEO Sam Altman’s meetings with senior executives from multiple chip manufacturers during his visit to Asia last year.
Altman visited top executives at companies such as TSMC and Samsung, proposing an ambitious plan to invest $7 trillion to build 36 new wafer fabs and data centers to drive the development of artificial intelligence. Altman envisioned that these fabs, funded by the United Arab Emirates, would produce AI chips, which OpenAI and other companies could use to build AI data centers.
The report highlighted that the scale of the investment Altman mentioned is equivalent to a quarter of the annual output of the U.S. economy. To meet OpenAI’s expansion needs for computing power, it would take several years to complete the necessary wafer fabs.
However, due to cost considerations, TSMC did not endorse Altman’s plan. TSMC executives considered Altman’s proposal too aggressive and risky. Even building a few more wafer fabs involves high risk due to the immense capital required, let alone 36 fabs.
How Much Does a Wafer Fab Cost? Hundreds of Billions of Dollars
In recent years, driven by the demand for AI models, the need for chips has surged, and wafer fabs have been expanding rapidly. However, as OpenAI’s experience shows building a wafer fab is no simple task. It faces challenges such as international dynamics, costs, and technological hurdles, with cost being the largest barrier.
The cost of a wafer fab primarily involves land and facility construction, equipment procurement, technology development and intellectual property, as well as operation and maintenance. Land and facility construction take up a significant portion, as a fab requires extensive land for building plants and basic infrastructure such as electricity, water supply, and communication.
On the equipment side, the purchase of lithography machines, etching machines, ion implanters, and thin-film deposition tools is a major expense, especially for advanced lithography machines, which are extremely costly.
Additionally, a wafer fab requires significant research and operational costs, including intellectual property, equipment maintenance, staff training, safety protocols, and environmental management, all of which demand continuous investment from manufacturers.
When all these factors are calculated, the cost of building a wafer fab is extremely high. Moreover, as chip manufacturing processes evolve, the cost of fabs continues to rise. The industry estimates that the cost of a modern fab is in the range of billions of dollars. For example, Intel’s two factories in Arizona are expected to cost $15 billion each, while Samsung’s fab in Taylor, Texas, is projected to cost $25 billion.
Regional Differences in Wafer Fab Costs
It’s also worth noting that the cost of building a wafer fab varies by region. In Asia, for example, due to a well-established supply chain, abundant talent, and policy support, the cost of building a fab is relatively lower. In regions like Europe, the U.S., and the Middle East, however, costs may be higher due to the need to import technology, train talent, and develop a complete supply chain.
(Photo credit: Intel)
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Samsung reported its third-quarter earnings today, and according to The Korea Economic Daily, the company’s operating profit was initially expected to exceed 10 trillion won, but the actual performance fell short of that target.
Reuters also reported that Samsung Electronics warned its third-quarter profit would fall short of market expectations, issuing an apology for the disappointing performance. The tech giant has been lagging behind its rivals in supplying high-end chips to Nvidia amid the booming AI market.
The Korea Economic Daily noted that Samsung’s operating profit for the third quarter reached 9.1 trillion won, a 274.5% increase from the same period last year. However, this figure still fell significantly short of the expected 10 trillion won. Sales for the quarter amounted to 79 trillion won, up 17.2% year-on-year. The Device Solutions (DS) division, responsible for semiconductor operations, saw its performance decline compared to the previous quarter due to one-off costs, including incentive provisions.
Although demand for memory chips such as servers and high-bandwidth memory (HBM) remained stable, factors like inventory adjustments by mobile clients and increased supply of legacy products from Chinese memory manufacturers negatively impacted performance, exacerbated by one-time costs and exchange rate effects. Additionally, the weaker-than-expected recovery in demand for Samsung’s flagship conventional DRAM products, particularly due to sluggish smartphone and PC markets, further hindered its results.
In the same report by The Korea Economic Daily, it was noted that in the HBM sector, Samsung has yet to make significant progress. The commercialization of its fifth-generation HBM, HBM3E, has been delayed, with the product still undergoing quality tests by NVIDIA. However, the Device Experience (DX) division saw improved performance due to strong flagship smartphone sales, and Samsung Display benefited from new product launches by key customers.
The Korea Economic Daily highlighted that analysts had forecast Samsung’s third-quarter operating profit to surpass 10 trillion won, with sales expected to reach around 81 trillion won, but both figures missed these projections.
Before Samsung’s earnings announcement, The Korea Times had reported that the market expected SK Hynix to see a substantial increase in operating profit driven by strong HBM demand, potentially outpacing Samsung’s semiconductor division.
Regarding Samsung’s HBM3E validation, TrendForce noted in a September press release that while Samsung entered the HBM3E market later, the company recently completed validation and has begun shipping its HBM3E 8Hi units. According to TrendForce’s latest research, Samsung, SK Hynix, and Micron submitted their first HBM3E 12Hi samples in the first half and third quarter of 2024, with ongoing validation processes. SK Hynix and Micron are progressing faster and are expected to complete validation by the end of this year.
(Photo credit: Samsung)
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South Korea’s two major memory chip manufacturers, Samsung Electronics and SK Hynix, are set to release their Q3 earnings reports (July to September) at the end of the month, with Samsung Electronics also announcing its financial forecast on October 8.
According to The Korea Times, the market expects SK Hynix to see a significant surge in operating profit driven by strong demand for high-bandwidth memory (HBM), potentially outperforming Samsung’s semiconductor division.
The Korea Times reports that SK Hynix’s Q3 operating profit is forecast to hit 6.76 trillion won (around $5 billion), with total revenue projected at 17.99 trillion won. If these estimates hold, SK Hynix may set a new record for quarterly operating profit, despite the broader challenges facing the global memory chip market.
On the other hand, Samsung Electronics does not break down individual business units in its earnings forecasts. However, the company’s Device Solutions (DS) division, which handles the memory chip business, is expected to contribute more than half of Samsung’s overall operating profit.
The market anticipates that Samsung Electronics will report an overall Q3 operating profit of 10.77 trillion won, with its DS division’s profit ranging between 5.2 trillion and 6.3 trillion won.
The Korea Times points out that SK Hynix could potentially surpass Samsung in operating profit by 400 billion to 1.5 trillion won, dealing a blow to Samsung’s long-standing dominance as the world’s top memory chipmaker.
There is growing speculation that SK Hynix may overtake Samsung in annual operating profit.
According to Business Korea, SK Hynix has begun mass production of the world’s first 12-layer HBM3E, following its earlier shipment of 8-layer HBM3E to Nvidia, the leading semiconductor company. The company plans to start supplying the 12-layer HBM3E within this year, further strengthening its market position.
TrendForce forecasts that by next year, HBM will account for 10% of total DRAM bit production and contribute more than 30% of DRAM market revenue. Moreover, HBM3E is expected to make up over 80% of the total HBM demand.
(Photo credit: SK Hynix)