The industry holds high expectations for photonic chips, which play a crucial role in data centers, especially in high-bandwidth and energy-efficient data transmission. With the growing demand for efficient data processing driven by the rise of artificial intelligence, cloud computing, and IoT devices, the research and development of photonic chips have become increasingly urgent.

China’s First Photonic Chip Pilot Line Launched in Wuxi

On September 25th, the first domestic photonic chip pilot line built by the Wuxi Photonic Chip Research Institute of Shanghai Jiao Tong University was officially launched. After the pilot line becomes operational, it is expected to reach an annual production capacity of 10,000 wafers. The first PDK will be released in the first quarter of 2025, providing external chip fabrication services.

The photonic chip pilot platform covers an area of 17,000 square meters, integrating research, production, and services. It is equipped with more than 100 top-tier international CMOS process machines, supporting a full closed-loop process for lithium niobate photonic chips, from lithography, thin film deposition, etching, wet processing, cutting, measurement, to packaging. The platform also supports other material systems like silicon and silicon nitride.

Jinan Achieves World’s First 12-Inch Lithium Niobate Crystal

in May of this year, Shandong Hengyuan Semiconductor Technology Co., Ltd. in Jinan successfully developed a 12-inch (300mm diameter) large-sized optical-grade lithium niobate crystal.

Shandong Hengyuan Semiconductor has been dedicated to the R&D of optoelectronic materials such as lithium niobate and lithium tantalate, as well as piezoelectric materials. Through technological advancements, the company has started mass production of 6-8 inch Z-axis and X-axis optical-grade lithium niobate crystals. Within three years, Hengyuan plans to increase its annual wafer production to 250,000 units.

Chinese Scientists Develop Mass-Produced New “Optical Silicon” Chips

In early May, the research team led by researcher Ou Xin at the Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, made a breakthrough in the preparation of lithium tantalate heterogeneously integrated wafers and high-performance photonic chips. They successfully developed a new type of “optical silicon” chip that can be mass-produced. The research results were published in Nature on May 8th.

Tsinghua University Team Releases AI Photonic Chip

In August, Tsinghua University announced that the research group led by Professor Fang Lu from the Department of Electronic Engineering and the team led by Academician Dai Qionghai from the Department of Automation pioneered a fully forward intelligent optical computing training architecture. They developed the “Taiji-II” optical training chip, enabling efficient and precise training of large-scale neural networks in optical computing systems. This research, titled “All-Forward Training of Optical Neural Networks,” was published in Nature.

The previously released Taiji-I, in April, achieved 879 T MACS/mm²area efficiency and 160 TOPS/W energy efficiency, marking the first time optical computing was applied to complex AI tasks such as natural scene recognition with thousands of categories and cross-modal content generation.

Chinese Team Successfully Develops Fully Programmable Topological Photonic Chip

In late May, the “Extreme Optics Innovation Research Team” from Peking University’s School of Physics, in collaboration with Researcher Yang Yan from the Institute of Microelectronics, Chinese Academy of Sciences, proposed and realized a fully programmable topological photonic chip based on large-scale integrated optics.

The chip built on a reconfigurable integrated optical micro-ring array, integrates 2,712 components in an area of just 11mm x 7mm. It successfully achieved the world’s first fully programmable optical artificial atomic lattice. The researchers also experimentally validated multiple topological phenomena on a single-chip platform, including dynamic topological phase transitions, multi-lattice topological insulators, statistical topological robustness, and Anderson topological insulators.

With silicon photonics emerging as a key enabler in the AI era, semiconductor giants have been accelerating their deployment in the technology. Now TSMC announces its latest breakthrough. According to a press release, by collaborating with EDA solution provider Ansys, the foundry leader has achieved over 10X speed-up of photonics simulation, powered by NVIDIA’s GPUs running on the Azure AI infrastructure of Microsoft.

Silicon PIC is a type of optical communications that enables data to travel farther and faster, which can be integrated to hyperscale data centers and IoT applications.

However, combining photonic and electronic circuits is a painstaking task requiring precise multiphysics design and fabrication. A minor misstep can create continuity challenges within chips, which can result in additional cost and timeline setbacks up to several months.

Therefore, to address challenges and harness the ultra-bandwidth potential of silicon PICs, TSMC partnered with Ansys to accelerate Lumerical FDTD simulations by leveraging Azure virtual machines powered by NVIDIA GPUs.

The press release notes that these Azure NC A100v4 VMs could facilitate the simulations, optimizing resources to achieve a cost-effective balance between performance and expense. Together, the companies achieved over 10X speed-up of Ansys Lumerical FDTD photonics simulation.

Moreover, running Lumerical FDTD simulations in the cloud allows designers to quickly identify optimal chip designs while addressing the multiphysics challenges of integrating photonic and electronic circuits, according to the press release.

It is worth noting that silicon photonics has been one of TSMC’s major focus in recent years. A previous report by Nikkei notes that TSMC aims to ready next-gen silicon photonics for AI in 5 years.

At the launch event of the Silicon Photonics Industry Alliance (SiPhIA) in early September, K.C. Hsu, Vice President of Integrated Interconnect & Packaging at TSMC, stated that with the massive computing demands and the large-scale data transmission in the AI era, silicon photonics plays an increasingly vital role, according to a report by the Economic Daily News.

Citing internal TSMC data, Hsu noted that by 2030, AI cloud services are expected to consume 3.5% of the world’s energy. However, with the assistance of silicon photonics and the co-packaged optics (CPO) technology, which is an advanced heterogeneous integration of optics and silicon on a single packaged substrate, the energy consumption per unit can be further reduced, according to the report.

Earlier in April, TSMC has announced that the company is developing Compact Universal Photonic Engine (COUPE) technology, which uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods.

According to its press release, TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as co-packaged optics (CPO) in 2026, bringing optical connections directly into the package.

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(Photo credit: Ansys)

While all eyes are on Intel’s restructuring plan, which features the foundry unit’s spin-off and the delay of Germany and Poland factories, there is another critical decision regarding its photonics business.

According to Intel’s announcement, the tech giant is moving Integrated Photonics Solutions (IPS) into its Data Center and Artificial Intelligence division (DCAI), as it tries to drive a more focused R&D plan that’s fully aligned with its top business priorities.

This shuffle seems to be reasonable, as earlier this year, Intel has achieved a milestone in integrated photonics technology for high-speed data transmission, and the two arenas seem to be inseparable.

A few months ago, Intel demonstrated the industry’s most advanced and first-ever fully integrated optical compute interconnect (OCI) chiplet co-packaged with an Intel CPU and running live data. According to Intel, the OCI chiplet represents a leap forward in high-bandwidth interconnect by enabling co-packaged optical input/output (I/O) in emerging AI infrastructure for data centers and high performance computing (HPC) applications.

A report by Photonics Spectra notes that Intel’s IPS division focuses on technologies such as light generation, amplification, detection, modulation, CMOS interface circuits, and package integration.

Here’s why this technology matters: As chipmakers advance Moore’s Law, increasing transistor density, signal loss during transmission becomes a significant issue because chips use electricity to transmit signals. Silicon photonics technology addresses this problem by using optical signals instead of electrical ones, allowing for high-speed data transmission, greater bandwidth, and faster data processing.

Intel has been developing silicon photonics technology for over 30 years. Since the launch of its silicon photonics platform in 2016, Intel has shipped over 8 million photonic integrated circuits (PICs) and more than 3.2 million integrated on-chip lasers, according to its press release. These products have been adopted by numerous large-scale cloud service providers.

In addition to Intel, rivals such as AMD and TSMC are also accelerating the development of next-generation silicon photonic solution.

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• [News] Venturing into Silicon Photonics, AMD Reportedly Seeks Partnerships in Taiwan
• [News] TSMC’s Latest Advancements in CFET, 3D Stacking, and Silicon Photonics

(Photo credit: Intel)

As silicon photonics has become a key technology in the AI era, semiconductor giants, including Intel and TSMC, have joined the battlefield. Now another tech giant has engaged in the war, while U.S. chip giant AMD is reportedly seeking silicon photonics partners in Taiwan, according to local media United Daily News.

According to the report, AMD has reached out to Taiwanese rising stars in the sector, including BE Epitaxy Semiconductor and best Epitaxy Manufacturing Company. The former focuses on the design, research and development of silicon photonics platforms, while the latter possesses MOCVD machines to produce 4-inch and 6-inch epitaxy wafers.

Regarding the rumor, AMD declined to comment. Recently, the AI chip giant announced a USD 4.9 billion acquisition of server manufacturer ZT Systems to strengthen its AI data center infrastructure, with the aim to further enhance its system-level R&D capability. Now it seems that AMD is also eyeing to set foot in the market, as silicon photonics is poised to be a critical technology in the future.

Earlier in July, AMD is said to establish a research and development (R&D) center in Taiwan, which will focus on several advanced technologies, including silicon photonics, artificial intelligence (AI), and heterogeneous integration.

Here’s why the technology matters: As chipmakers keep pushing the boundaries of Moore’s Law, leading to increased transistor density per unit area, signal loss issues inevitably arise during transmission since chips rely on electricity to transmit signals. Silicon photonics technology, on the other hand, by replacing electrical signals with optical signals for high-speed data transmission, successfully overcomes this challenge, achieving higher bandwidth and faster data processing.

On September 3, a consortium of more than 30 companies, including TSMC, announced the establishment of the Silicon Photonics Industry Alliance (SiPhIA) at SEMICON.

According to a previous report by Nikkei, TSMC and its supply chain are accelerating the development of next-generation silicon photonic solutions, with plans to have the technology ready for production within the next three to five years.

AMD’s major rival, NVIDIA, is reportedly collaborating with TSMC to develop optical channel and IC interconnect technologies.

On the other hand, Intel has been developing silicon photonics technology for over 30 years. Since the launch of its silicon photonics platform in 2016, Intel has shipped over 8 million photonic integrated circuits (PICs) and more than 3.2 million integrated on-chip lasers, according to its press release. These products have been adopted by numerous large-scale cloud service providers.

Interestingly enough, Intel has also been actively collaborating with Taiwanese companies in the development of silicon photonics, United Daily News notes. One of its most notable partners is LandMark Optoelectronics, which supplies Intel with critical upstream silicon photonics materials, such as epitaxial layers and related components.

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• [News] Silicon Photonics Reshapes the Future; TSMC, ASE Ready to Seize Market Share
• [News] TSMC’s Latest Advancements in CFET, 3D Stacking, and Silicon Photonics

(Photo credit: AMD)

If you happen to be a technology enthusiast, June would certainly be a month to watch. NVIDIA CEO Jensen Huang, joined by AMD CEO Lisa Su, visited Taiwan to announce their product roadmaps in COMPUTEX 2024. NVIDIA unveiled its new generation Rubin architecture, indicating that the R series products are expected to go into mass production in the fourth quarter of 2025.

On the other hand, AMD introduced its Ryzen AI 300 Series processors with the world’s most powerful Neural Processing Unit (NPU) for next-gen AI PCs, featuring a new Zen 5 CPU, as well as its latest AI chips, MI325X and MI350.

Interestingly enough, on 4 June, the world’s largest semiconductor foundry, TSMC, held its shareholders’ meeting in Hsinchu, Taiwan. When asked about the company’s relationships with NVIDIA and AMD, President C.C. Wei has reaffirmed TSMC’s strong relationships with the two tech giants, saying that the company will prosper with its clients.

What will be the highlights for TSMC’s progress in advanced logic process, and what are some of the most advanced products introduced in COMPUTEX made with TSMC’s advanced nodes? Please proceed to find out more. For now, TSMC’s 3nm seems to be the most popular node.

N3 Family

TSMC’s N3E (the more cost-effective second generation of the 3nm process) entered mass production in the fourth quarter of 2023. On the other hand, N3P (a more advanced version) is scheduled to enter mass production in the second half of 2024. Its yield performance is close to that of N3E, while customer product designs have already been tape-out.

TSMC states that due to N3P’s superior performance, better power consumption and area (PPA) characteristics, most 3nm products will eventually adopt the node. In the future, the industry may expect to see more high-end products manufactured with 3nm.

Regarding capacity, driven by the strong demand from HPC and mobile phone, TSMC has tripled its 3nm capacity in 2024 compared to that of 2023. However, as it is still not enough, the world’s largest semiconductor foundry has been striving to meet customer demand.

Intel’s Lunar Lake/ Arrow Lake

At COMPUTEX 2024, Intel CEO Pat Gelsinger introduced Lunar Lake, its latest AI PC chip, and thank its friend “TSMC” for their full support.

Starting Q3 2024 in time for the holiday season, Lunar Lake will power more than 80 new laptop designs across more than 20 original equipment manufacturers.

In a previous report by Wccftech, Gelsinger stated that Intel has collaborated with TSMC to power up its next-gen CPUs, adopting N3B, the first-generation 3nm process, for Lunar Lake and Arrow Lake.

NVIDIA’s Rubin

On the other hand, NVIDIA’s Rubin GPU architecture is now official: the Rubin GPU will feature 8 HBM4, while the Rubin Ultra GPU will come with 12 HBM4 chips, noted by Jensen Huang, CEO of NVIDIA.

Per a report from Wccftech, NVIDIA’s Rubin GPU is expected to utilize TSMC’s CoWoS-L packaging technology, along with its N3 process. Moreover, NVIDIA will use next-generation HBM4 DRAM to power its Rubin GPU.

Regarding NVIDIA’s previous GPUs, according to Commercial Times’ report, H200 and B100 reportedly are said to adopt TSMC’s 4-nanometer and 3-nanometer processes, respectively.

AMD’s MI 325X/ MI350

On 3 June, AMD CEO Lisa Su stated that the company’s relationship with TSMC is “very strong,” even as rumors have been circulating about a potential partnership with Samsung, TSMC’s main competitor.

AMD unveiled the company’s latest AI chip, MI325X, at the opening of COMPUTEX Taipei. Su emphasized that the MI325X boasts 30% faster computing speed compared to NVIDIA’s H200.

Furthermore, she also announced that AMD will release MI350 in 2025, which will be manufactured with TSMC’s 3nm process, while MI400 is expected to follow, launched in 2026.

When asked if AMD intended to procure chips manufactured using Samsung’s 3-nanometer (3nm) gate-all-around (GAA) process, Su reiterated AMD’s commitment to utilizing “the most advanced technology,” saying that AMD is certainly going to use 3 nm, 2 nm, and beyond. She also confirmed that there are several 3nm products currently being developed in collaboration with TSMC.

In addition to TSMC’s collaboration with clients on 3nm, this article also curates TSMC’s progresses on its 2nm node and other advanced processes. More information below:

N2 Family

The N2 process utilizes nanosheet transistors, thus would be able to offer superior energy efficiency. Currently, TSMC’s 2nm technology is progressing smoothly, with nanosheet conversion performance reaching the target of 90%, indicating that the yield exceeds 80%. Mass production is expected in 2025.

In the future, TSMC states that more members of the N2 family will emerge, including applications like N2P and N2X.

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• [News] TSMC’s Advanced Packaging Capacity Fully Booked by NVIDIA and AMD Through Next Year
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(Photo credit: TSMC)