TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company’s 2024 North America Technology Symposium.

TSMC debuted the TSMC A16TM technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW™) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

“We are entering an AI-empowered world, where artificial intelligence not only runs in data centers, but PCs, mobile devices, automobiles, and even the Internet of Things,” said TSMC CEO Dr. C.C. Wei. “At TSMC, we are offering our customers the most comprehensive set of technologies to realize their visions for AI, from the world’s most advanced silicon, to the broadest portfolio of advanced packaging and 3D IC platforms, to specialty technologies that integrate the digital world with the real world.”

New technologies introduced at the symposium include:

TSMC A16TM Technology: With TSMC’s industry-leading N3E technology now in production, and N2 on track for production in the second half of 2025, TSMC debuted A16, the next technology on its roadmap.

A16 will combine TSMC’s Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks.

Compared to TSMC’s N2P process, A16 will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15- 20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products.

TSMC NanoFlexTM Innovation for Nanosheet Transistors: TSMC’s upcoming N2 technology will come with TSMC NanoFlex, the company’s next breakthrough in design-technology co optimization. TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Customers are able to optimize the combination of short and tall cells within the same design block, tuning their designs to reach the optimal power, performance, and area tradeoffs for their application.

N4C Technology: Bringing TSMC’s advanced techynology to a broader range of of applications, TSMC announced N4C, an extension of N4P technology with up to 8.5% die cost reduction and low adoption effort, scheduled for volume production in 2025.

N4C offers area-efficient foundation IP and design rules that are fully compatible with the widely-adopted N4P, with better yield from die size reduction, providing a cost-effective option for value-tier products to migrate to the next advanced technology node from TSMC.

CoWoS, SoIC, and System-on-Wafer (SoW): TSMC’s Chip on Wafer on Substrate (CoWoS) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and high-bandwidth memory (HBM) stacks side by side on one interposer. At the same time, our System on Integrated Chips (SoIC) has established itself as the leading solution for 3D chip stacking, and customers are increasingly pairing CoWoS with SoIC and other components for the ultimate system-in-package (SiP) integration.

With System-on-Wafer, TSMC is providing a revolutionary new option to enable a large array of dies on a 300mm wafer, offering more compute power while occupying far less data center space and boosting performance per watt by orders of magnitude.

TSMC’s first SoW offering, a logic only wafer based on Integrated Fan-Out (InFO) technology, is already in production. A chip-on-wafer version leveraging CoWoS technology is scheduled to be ready in 2027, enabling integration of SoIC, HBM and other components to create a powerful wafer-level system with computing power comparable to a data center server rack, or even an entire server.

Silicon Photonics Integration: TSMC is developing Compact Universal Photonic Engine (COUPE ) technology to support the explosive growth in data transmission that comes with the AI boom. COUPE uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods.

TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as co-packaged optics (CPO) in 2026, bringing optical connections directly into the package.

Automotive Advanced Packaging: After introducing the N3AE “Auto Early” process in 2023, TSMC continues to serve our automotive customers’ needs for greater computing power that meets the safety and quality demands of the highway by integrating advanced silicon with advanced packaging.

TSMC is developing InFO-oS and CoWoS-R solutions for applications such as advanced driver assistance systems (ADAS), vehicle control, and vehicle central computers, targeting AEC-Q100 Grade 2 qualification by fourth quarter of 2025.

(Photo credit: TSMC)

As generative AI applications fuel the era of high computing power, Foxconn’s connector subsidiary FIT announced on March 25th a cross-industry collaboration with MediaTek. Together, they will develop next-generation high-speed connectivity solutions, specifically Co-Packaged Optics (CPO), aiming to capitalize on the booming silicon photonics market.

According to a report from Economic Daily News, FIT and MediaTek have previously collaborated as upstream and downstream partners, with FIT being a leading manufacturer of custom ASIC sockets and having significant capacity for cooperation with upstream IC design firms.

This collaboration may mark their first joint venture in developing next-generation optical communication products, aiming to create CPO high-speed connectivity solutions using ASIC platforms and silicon photonics technology.

Foxconn Group Collaborates with MediaTek Across Industries

Industry sources cited by the report suggest that traditional data center transmission occurs on PCBs, whereas the CPO architecture is situated on the substrate, integrating optical communication components with switch into a module installed in a slot. This configuration shortens data transmission paths, reducing transmission losses and power consumption.

With the commercialization of generative AI, large language models require extensive computation within data centers, demanding high transmission rates to enhance operational efficiency. Traditional data transmission methods face significant signal loss, prolonging model training times and increasing power consumption. Consequently, the emergence of new network communication technology, CPO, addresses these challenges.

FIT asserts that CPO represents the next-generation optical communication transmission architecture, capable of shortening transmission paths, reducing transmission losses and signal delays, thereby providing more robust connectivity for AI computing and applications. It can be combined with the company’s existing optical communication products of 800G and 1.6T, forging ahead with next-generation network communication technology.

Through collaboration with MediaTek, they aim to offer customers more diverse and efficient connectivity solutions, driving the development of the era of high computational power.

MediaTek, as per the report, emphasized its commitment to adopting the industry’s most advanced processes, packaging technologies, and architectures, providing customers with diverse ASIC design platforms.

This initiative aims to offer the latest and comprehensive solutions to the rapidly growing data center and server markets. Collaborating with FIT on CPO further enhances their ability to deliver next-generation high-speed transmission solutions, thereby creating new market opportunities for customers.

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(Photo credit: Foxconn)

MediaTek has reportedly made its foray into the booming field of Heterogeneous Integration Co-Packaged Optics (CPO), announcing on March 20th a partnership with optical communications firm Ranovus to launch a customized Application-Specific Integrated Circuit (ASIC) design platform for CPO. This platform is reported to provide advantages such as low cost, high bandwidth density, and low power consumption, expanding MediaTek’s presence in the thriving markets of AI, Machine Learning (ML), and High-Performance Computing (HPC).

According to its press release, on the eve of the 2024 Optical Fiber Communication Conference (OFC 2024), MediaTek announced the launch of a new-generation customized chip design platform, offering heterogeneous integration solutions for high-speed electronic and optical signal transmission interfaces (I/O).

MediaTek stated that it will be demonstrating a serviceable socketed implementation that combines 8x800G electrical links and 8x800G optical links for a more flexible deployment. It integrates both MediaTek’s in-house SerDes for electrical I/O as well as co-packaged Odin® optical engines from Ranovus for optical I/O.

As per the same release, leveraging the heterogeneous solution that includes both 112G LR SerDes and optical modules, this CPO demonstration is said to be delivering reduced board space and device costs, boosts bandwidth density, and lowers system power by up to 50% compared to existing solutions.

MediaTek emphasizes that its ASIC design platform covers all aspects from design to production, offering a comprehensive solution with the latest industry technologies such as MLink, UCIe’s Die-to-Die Interface, InFO, CoWoS, Hybrid CoWoS advanced packaging technologies, PCIe high-speed transmission interfaces, and integrated thermals and mechanical design.

“The emergence of Generative AI has resulted in significant demand not only for higher memory bandwidth and capacity, but also for higher I/O density and speeds, integration of electrical and optical I/O is the latest technology that allows MediaTek to deliver the most flexible leading edge data center ASIC solutions.” said Jerry Yu, Senior Vice President at MediaTek.

As per Economy Daily News citing Industry sources, they have predicted that as the next-generation of optical communication transitions to 800G transmission speeds, the physical limitations of materials will necessitate the use of optical signals instead of electronic signals to achieve high-speed data transmission. This, reportedly, will lead to a rising demand for CPOs with optical-to-electrical conversion capabilities, becoming one of the new focal points for semiconductor manufacturers to target.

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(Photo credit: MediaTek)

Kevin Zhang, Senior Vice President of Business Development at TSMC, introduced the company’s latest technologies at the International Solid-State Circuits Conference (ISSCC) 2024. According to TechNews citing from the speech, Zhang shared insights into future technological advancements, prospects for advanced processes, and the latest semiconductor technologies needed in various fields.

Zhang noted that since the introduction of ChatGPT and Wi-Fi 7, a lot of advanced semiconductor are required, as we are entering an accelerated growth period for semiconductor going forward.

In the automotive sector, the industry is undergoing a revolution, with many suggesting that new vehicles will be software-defined. However, Zhang believes it’s more about silicon-defined because software needs to run on silicon, driving the future of autonomous driving capabilities.

CFET (Complementary Field-Effect Transistor)

In terms of technology, Transistor remain at the heart of the innovation, silicon innovation. It has shifted from geometry reduction to architectural innovation and the use of new materials. Moving from 16-nanometer FinFET to today’s 2-nanometer Nano Sheet technology represents significant progress in high-performance computing and architectural innovation.

What’s next? The answer is CFET.

Kevin Zhang explained that CFET involves stacking nMOS and pMOS on top of each other, significantly improving component currents and increasing transistor density by 1.5 to 2 times.

Alternatively, efforts are being made to create higher-performance switching devices from low-dimensional materials such as 2D materials, surpassing today’s devices or transistors.

Kevin Zhang also showcased that TSMC has successfully fabricated CFET architectures in the laboratory, stating, “This is a real integrated device that has been fabricated in our lab. Here, you see the transistor IV curve. They are beautiful curves. So, this is a significant milestone in terms of continuing to drive the innovation of the transistor architecture.”

However, as the geometry of the transistor shrinks, it becomes increasingly difficult and costly. This necessitates collaboration between process development teams and design research to achieve optimal benefits, known as “Design-Technology Co-Optimization” (DTCO).

In addition, TSMC has introduced FINFLEX technology, enabling chip designers to choose and mix the best fin structures to support each critical functional block, achieving optimal performance, density, and power consumption.

Another example of DTCO is Static Random Access Memory (SRAM). SRAM has scaled from 130 nanometers to the current 3 nanometers, and TSMC has achieved a over 100x density improvement, a result of collaboration or combination of a process innovation and adoption of the more advanced design technique.

Nevertheless, the essence or the objective of this technology scaling is for “energy efficient compute,” as Kevin Zhang expressed. He stated that in the entire semiconductor industry, TSMC has come a long way, and this progress has made today’s AI possible.

• Advancements in HPC/AI Technology Platforms: 3D Stacking, Silicon Photonics, CPO

Whether it’s GPUs, TPUs, or customized ASICs, they all feature this particular integration scheme. Currently, the mainstream is 2.5D packaging. However, to meet future high-performance computing demands, this platform needs significant enhancement, requiring higher density and lower power consumption computation.

Therefore, stacking is needed, including integrating many memory bandwidths and HBM into the package, while considering issues such as power supply, I/O, and interconnect density.

Consequently, Kevin Zhang stated that bringing “silicon photonics into packaging” is the future direction. However, this will face many challenges, such as Co-Packaged Optics (CPO) closer to the electronic side.

1. 3D Stacking

When it comes to 3D stacking, Kevin Zhang presented a diagram and explained that to achieve higher interconnect density, specifically Chip-to-Chip connections, 3D stacking allows the bonding pitch to scale to just a few micrometers, achieving interconnect density like monolithic. “That’s why the 3D (stacking) is the future,” he concluded.

2. Silicon Photonics / Co-Packaged Optics (CPO)

Kevin Zhang pointed out that while electronics excel at computation, photons are better for signaling or communication. He illustrated that if a 50 terabyte switch, an all-electronic copper system were used, it would consume 2,400 W.

The current solution involves using pluggable modules, which can save 40% of power (> 1500W). However, as the need for higher-speed signals and larger bandwidths increases in the future, this solution falls short. Therefore, integrating silicon photonics technology is necessary to introduce photon capabilities.

• Automotive Technology

1. Pursuing Low DPPM

Fundamentally, the latest automotive technologies require significant computational power, but power consumption is becoming a concern, especially for battery-powered vehicles.

Kevin Zhang states that automotive semiconductor technology has lagged behind consumer or HPC technologies by several generations due to stringent safety requirements. The DPPM (Defects Per Million) for automotive applications must be close to zero.

Therefore, fabs, semiconductor manufacturers, and automotive designers must collaborate more closely to accelerate this pace. He also promises, “you will see 3 nanometer in your car before long.”

2. MRAM/RRAM

As automotive transitions to a domain architecture, MCUs (Microcontroller Units) become increasingly important and require advanced semiconductor technology to provide computational capabilities.

Traditional MCUs mostly rely on floating-gate technology, but this technology encounters bottlenecks below 28 nanometers. Fortunately, the industry has invested in new memory technologies, including new non-volatile memories such as Magnetic Random Access Memory (MRAM) or Resistive Random Access Memory (RRAM).

Therefore, transitioning from MCU to MRAM or RRAM-based technologies helps drive continuous technology scaling from 28 nanometers to 16 nanometers, or even 7 nanometers.

• Sensor and Display: CIS (CMOS Image Sensors)

Sensor technology has evolved from simple 2D designs and single layer design to intelligent systems with 3D wafer stacking, essentially layering the signal processing on top of the sensing layer.

Kevin Zhang also mentioned, “our technologies already start investing, researching on the multi-layer design.”

Engaging in three or more layer designs allows for the optimization of pixels, continuing the trend of scaling pixel sizes while meeting resolution requirements and achieving optimal sensing capabilities simultaneously.

Another example is AR (Augmented Reality) and VR (Virtual Reality), where separating memory layers and stacking them onto other logic chips can effectively reduce size while maintaining high-performance demands.

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(Photo credit: TSMC)

Japanese telecommunications operator NTT is reportedly collaborating with American chipmaker Intel and other semiconductor manufacturers to research large-scale production of next-generation semiconductor technology, which involves significantly reducing power consumption using optical technology.

According to a report from Nikkei, SK Hynix is also set to participate in this initiative, expected to counter China through collaborative research and development strategies.

Meanwhile, the Japanese government will provide approximately JPY 45 billion in support. As cited by Nikkei quoting Japan’s Ministry of Economy, Trade, and Industry, Japan can lead the world in this technology as part of its strategy to revitalize the national semiconductor industry.

These companies are reportedly aiming to develop equipment manufacturing technology that integrates light with semiconductors and memory technology capable of storing data at Terabit-class speeds by the fiscal year 2027. Intel will provide technical development suggestions, aiming to reduce power consumption by 30-40% compared to conventional products.

As semiconductor scaling reaches physical limits, as per a report from TechNews, the industry is turning towards light. When combined with semiconductors, known as silicon photonics, it is expected to significantly reduce energy consumption. This technology is also seen as potentially game-changing for the semiconductor industry.

Signals received through optical communication is converted into electrical signals by specialized equipment, which are then transmitted to data center servers. Semiconductors within the servers then exchange electrical signals to process computations and memory. With the proliferation of AI and the need to process massive amounts of data, the demand for optical technology is anticipated to increase.

The integration of silicon photonics still presents numerous challenges, primarily concerning interface communication protocols. Consequently, synchronization in communication among semiconductor manufacturers is essential for the realization of silicon photonics technology.

Therefore, NTT aims to coordinate necessary technologies through collaboration with Intel and SK Hynix.

NTT holds a global leadership position in integrating optical and electronic technologies, having successfully pioneered the foundational technology of using light for transistor circuits. This achievement was published in the British scientific journal “Nature Photonics” in 2019, leading to the introduction of the IOWN (Innovative Optical and Wireless Network) fully optical network based on this technology.

(Photo credit: Intel)