Samsung Electronics is ramping up its entry into the semiconductor glass substrate market by advancing its equipment procurement and installation to September, with trial production slated to begin in the fourth quarter, one quarter earlier than originally planned. According to a report from South Korean media outlet ETNews, Samsung Electronics aims to commence mass production of glass substrates for high-end System-in-Package (SiP) applications starting in 2026.

In order to manufacture highly complex multi-chiplet SiPs, Samsung has decided to expedite the trial production schedule at its Sejong plant in South Korea to gain more expertise in glass substrate manufacturing. Samsung’s competitor, Intel, also plans to offer packaging technology on glass substrates in the future.

Reportedly, Samsung Electronics plans to have all necessary equipment installed on the trial production line by September and commence operations in the fourth quarter. Partners for the trial production line include companies such as Philoptics, Chemtronics, Joongwoo M-Tech, and Germany’s LPKF, which will provide equipment components.

According to a report from Tom’s Hardware, Compared to traditional organic substrates, glass substrates offer significant advantages, including excellent flatness, which enhances exposure and focusing capabilities, as well as outstanding dimensional stability suitable for next-generation chip interconnects with multiple small chips. Additionally, glass substrates exhibit better thermal and mechanical stability, making them suitable for high-temperature durable applications in data centers.

Intel has been developing glass substrates for nearly a decade and plans to introduce commercial products by 2030. Intel believes that the characteristics of glass substrates will significantly increase interconnect density, which is crucial for efficient power transmission and signal routing in advanced SiP technology.

Previously, Intel also elaborated on its progress on the glass-based substrate packaging technology. According to Intel’s previous press release, glass substrates can tolerate higher temperatures, offer 50% less pattern distortion, and have ultra-low flatness for improved depth of focus for lithography as well as the dimensional stability needed for extremely tight layer-to-layer interconnect overlay.

As a result of these distinctive properties, a 10x increase in interconnect density is possible on glass substrates. Furthermore, improved mechanical properties of glass enable ultra-large form-factor packages with very high assembly yields.

Meanwhile, Absolics, a subsidiary of SKC America, aims to start production of glass substrates for customers as early as the second half of 2024.

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• [News] Samsung Bullish on Glass Substrate Applications, Setting Up Production Line for Mass Production Starting in 2026
• [News] Glass Substrates in Advanced Packaging With Intel Leads, TSMC Quietly Innovates

(Photo credit: Intel)

The semiconductor industry enters the era of integration. Various foundries are focusing on advanced packaging technologies, but the terminology surrounding advanced packaging can be daunting. This article aims to explain these terms in the simplest way possible.

According to a report from TechNews, currently, there are two main trends in advanced packaging: heterogeneous integration and chiplets.

In fact, the concept of “heterogeneous integration” has been developing for many years and is not exclusive to advanced packaging. It is not only used for the integration of heterogeneous chiplets but also for integrating other non-chip active/passive components into a single package, which is the technology commonly used in traditional Outsourced Semiconductor Assembly and Test Services(OSATs).

• Heterogeneous Integration = Big Building Blocks? Advanced Packaging = Small Building Blocks? 

In the simplest terms, “heterogeneous integration” can be likened to building with large building blocks, while “advanced packaging” is akin to assembling with small building blocks. Some manufacturers, like traditional Outsourced Semiconductor Assembly and Test Services(OSATs), excel in stacking large blocks, such as logic circuits, radio frequency circuits, MEMS (Micro-Electro-Mechanical Systems), or sensors, onto a IC substrate. The stacking of these different large blocks represents the concept of heterogeneous integration.

On the other hand, some blocks are too small to stack effectively, requiring assistance from advanced packaging, typically provided by semiconductor foundries.

Advanced packaging also encompasses 2.5D packaging and 3D packaging. Using the metaphor of building blocks, the former involves horizontally stacking small building blocks on a interposer, while the latter involves vertically stacking small building blocks with interconnection facilitated through Through-Silicon Vias (TSVs), which are ultra-small building blocks.

It’s important to emphasize that stacking blocks is a conceptual representation, and the distinction between large and small blocks is relative. The analogy above refers to heterogeneous integration in traditional packaging, and heterogeneous integration in advanced packaging follows a similar concept, but with even smaller building blocks.

• SoC / SiP / Heterogeneous Integration / Chiplet

With this concept in mind, let’s discuss the applications of heterogeneous integration in advanced packaging:

Among the various packaging types, SoC (System On Chip) involves integrating different chips such as processors and memory, with different functions, redesigned and fabricated using the “same process,” integrated onto a single chip, resulting in a final product with only one chip.

On the other hand, SiP (System in Package) involves connecting multiple chips with “different processes” through “heterogeneous integration” technology, integrated within the same packaging module. Therefore, the final product will be a system with many chips on it, resembling the stacking of different-sized building blocks mentioned earlier.

Therefore, heterogeneous integration refers to integrating different and separately manufactured components (heterogeneous) into higher-level assemblies. These components include blocks of different sizes, such as MEMS devices, passive components, logic chips, and more.

However, at a certain point, for the sake of process development, researchers found that separating components at the right time might facilitate miniaturization. Hence, chiplet was born.

• Is Chiplet the Fusion of Heterogeneous Integration and Advanced Processes?

As demands for ICs become increasingly complex, the size of SoC chips continues to grow. However, cramming too many components onto a limited substrate poses significant challenges, including heightened process complexity and reduced yield.

Hence, the concept of chiplets emerged, advocating for the segmentation of SoC functionalities, such as data storage, computation, signal processing, and data flow management, into smaller individual chips. These chiplets are then integrated through packaging to form a interconnected network.

It’s worth noting that Chiplets are essentially chips, whereas SiP refers to the packaging format. Chiplet architecture enable the reduction of individual chip sizes, simplify circuit design, overcome manufacturing difficulties and yield issues, and offer greater design flexibility.

• Advanced Packaging Technologies in Foundries

Currently, advanced packaging can be broadly categorized into three main types: Wafer-Level Packaging (WLP), 2.5D Packaging, and 3D Packaging. Traditional packaging involves cutting wafers into chips before packaging, while advanced packaging entails packaging the silicon wafer before cutting, requiring subsequent stacking processes in fabs. Therefore, the technology is primarily the responsibility of fabs.

Traditional packaging involves cutting wafers into chips before packaging. Advanced packaging, starting from wafer-level packaging, involves packaging silicon wafers before cutting, and subsequent stacking requires wafer fabrication processes.

Therefore, this article will delve into advanced packaging technologies offered by the three major foundries, with a focus on 2.5D and 3D packaging.

• 2.5DIC / 3DIC Packaging

To further explain using building blocks, the difference between 2.5D and 3DIC packaging lies in the “stacking method.”

In 2.5D packaging, processors, memory, or other chips are stacked horizontally on a silicon interposer using a flip-chip method, with micro bumps connecting different chip’s electronic signals. Through silicon vias (TSVs) in the interposer link to the metal bumps below, then packaged onto the IC substrate, creating tighter interconnections between the chips and the substrate.

In a side view, although the chips are stacked, the essence remains horizontal packaging, with the chips positioned closer together and allowing for smaller chip sizes. Additionally, this is a form of “heterogeneous integration” technology.

3D packaging involves stacking multiple chips (face down) together, directly using through-silicon vias to stack them vertically, linking the electronic signals of different chips above and below, achieving true vertical packaging. Currently, more and more CPUs, GPUs, and memories are starting to adopt 3D packaging technology.

• Hybrid Bonding

Hybrid bonding is one of the die bonding techniques used in advanced chip packaging processes. One of the commercially available technologies in this domain is the “Cu-Cu hybrid bonding.”

In traditional wafer bonding processes, there are interfaces between copper and dielectric materials. With “Cu-Cu hybrid bonding,” metal contacts are embedded within the dielectric material. Through a thermal treatment process, these two materials are bonded together, utilizing the atomic diffusion of copper metal in its solid-state to achieve the bond. This approach addresses challenges encountered in previous flip-chip bonding process.

Compared to flip-chip bonding, hybrid bonding offers several advantages. It allows for achieving ultra-high I/O counts and longer interconnect lengths. By using dielectric material for bonding instead of bottom fillers, the cost of filling is eliminated.

Additionally, hybrid bonding results in minimal thickness compared to chip-on-wafer bonding. This is particularly beneficial for future developments in 3D packaging, where stacking multiple layers of chips is required, as hybrid bonding can significantly reduce the overall thickness.

• Advanced Packaging Moves Towards the Era of Heterogeneous Integration

As the semiconductor industry enters the “post-Moore’s Law era,” the development focus of advanced packaging is gradually shifting from 2D planar structures to 3D stacking and from single-chip designs to multi-chip configurations. Therefore, “heterogeneous integration” will play a crucial role in future advanced packaging.

Currently, prominent companies such as TSMC, Samsung, and Intel are intensifying their research and development efforts and capacity expansions in this field, introducing their innovative packaging solutions.

With ongoing technological advancements and innovations, advanced packaging and heterogeneous integration will play increasingly vital roles in propelling the semiconductor industry towards greater heights, meeting the complex and diverse demands of future electronic devices.

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• [News] The Era of Heterogeneous Integration Approaches: Who Shall Dominate the Advanced Packaging Field?

(Photo credit: Intel)

As semiconductor fabrication technologies continue to advance, the number of transistors in integrated circuits (ICs) has steadily increased. Initially, ICs contained only tens of transistors, but as technology progressed, ICs integrating hundreds of thousands of transistors enabled the realization of 3D animation. ICs with millions of transistors allowed computers to enter households, and today, ICs with hundreds of billions or even trillions of transistors enable digital technology to connect the entire world, profoundly impacting people’s lives.

Over the past 65 years, semiconductor fabrication processes have rapidly evolved, driven by Moore’s Law, gradually reshaping society. However, in recent years, semiconductor processes have approached physical limits, and the failure of Moore’s Law has been a topic of concern. In response, 3D IC stacking and heterogeneous integration technologies have emerged as promising solutions.

3D Stacking Trends

With the rapid development of applications such as AI, AR/VR, and 8K, a significant demand for computation is expected to continue, particularly driving parallel computing systems capable of handling vast amounts of data in a short time. As semiconductor processes slow down, 3D packaging has become an effective means to extend Moore’s Law and enhance IC computing performance.

3D packaging technology offers numerous advantages over traditional 2D packaging. It enables size reduction, with silicon interposer efficiency exceeding 100%, improved connectivity, reduced parasitic effects, lower power consumption, lower latency, and higher operating frequencies. These advantages, along with various benefits of 3D integration and interconnection technologies, make 3D packaging a development direction pursued by major players in the industry.

imec’s Vision for 3D Technology

In the field of 3D stacking technology, imec (imec, the Belgian Interuniversity Microelectronics Centre) defines four categories of 3D integration solutions: 3D-SIP, 3D-SIC, 3D-SOC, and 3D-IC, each requiring different process solutions and 3D integration techniques. Eric Beyne, VP R&D, Director 3D System Integration Program at imec specifically notes that concerning 3D interconnection technology, the scope of 3D interconnection will extend from stack packaging below 1 millimeter (mm), such as Package-on-Package (POP), to below 100 nanometers (nm) with true 3D ICs using transistor stacking, surpassing an interconnect density of 108/mm².

imec identifies three key elements in 3D integration technology: Through-Silicon Via (TSV), die-to-die and die-to-wafer stacking and interconnection, and wafer-to-wafer bonding technology. Beyne points out that TSV miniaturization technology continues to evolve. However, regarding “interconnect gaps,” as TSVs further shrink, microbump technology may struggle to meet higher interconnection demands, making cu-cu hybrid bonding technology a focus of development.

▲The image shows imec’s 3D interconnect technology roadmap, illustrating that as packaging technology continues to advance, node sizes shrink, and density further increases in 3D packaging. (Source：ISSCC 2021)

3D-SIP

System-in-Package (SIP), a form of system-level packaging, connects multiple chips that undergo different fabrication processes and preliminary packaging using heterogeneous integration techniques, integrating them within the same packaging shell. 3D-SIP involves vertically stacking multiple SIP chips, including packaging interconnects, fan-out wafer-level packaging, and solder ball bonding.

▲The image on the left is a schematic diagram of 3D-SIP packaging, where the connection points on both sides of the PCB board link the chips that have undergone initial packaging from top to bottom. The image on the right is an actual product illustration. (Source：TrendTorce (Left)，ISSCC 2021(Right))

Currently, the connection pitch in existing solutions is approximately 400 micrometers (µm). imec’s research aims to increase the interconnectivity of such SIPs by 100 times, reducing connection pitch to 40 µm. Common applications of 3D-SIP packaging include RF FEMs, TWS Barbuds SoCs.

3D-SIC

The second category, 3D-SIC (Stacking IC), involves the stacking of individual chips on top of each other. 3D-SIC is achieved by stacking chips on an interposer or wafer, with the finished chips bonded to the top of the wafer. Chips are interconnected through TSVs and microbumps, with industry solutions achieving pitch sizes as small as 40 µm. The technology is applied to products like 3D-DRAM and logic chips, connected alongside optical I/O units on the interposer. Currently, 3D-SIC technology is widely used in High-Bandwidth Memory (HBM) manufacturing.

▲The image depicts a schematic diagram of 3D-SIC, which utilizes cu-cu hybrid bonding technology to connect the upper and lower layers of ICs. (Source:imec)

3D stacking packaging is leading the global semiconductor industry, and imec has outlined a development blueprint focused on reducing interconnection pitch and increasing contact density per unit area, positioning 3D stacking as a solution to continue Moore’s Law amid slowing semiconductor processes.

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This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: TSMC )

Semiconductor process technology is nearing the boundaries of known physics. In order to continually enhance processor performance, the integration of small chips (chiplets) and heterogeneous Integration has become a prevailing trend. It is also regarded as a primary solution for extending Moore’s Law. Major industry players such as TSMC, Intel, Samsung, and others are vigorously developing these related technologies.

What are SoC, SiP, and Chiplet?

To understand Chiplet technology, we must first clarify two commonly used terms: SoC and SiP. SoC (System on Chip) involves redesigning multiple different chips to utilize the same manufacturing process and integrating them onto a single chip. On the other hand, SiP (System in Package) connects multiple chips with different manufacturing processes using heterogeneous integration techniques and integrates them within a single packaging form.

Chiplet technology employs advanced packaging techniques to create a SiP composed of multiple small chips. It integrates small chips with different functions onto a single substrate through advanced packaging techniques. While Chiplets and SiPs may seem similar, Chiplets are essentially chips themselves, whereas SiP refers to the packaging form. They have differences in functionality and purpose.

Chiplets: Today’s Semiconductor Development Trend

The design concept of Chiplet technology offers several advantages over SoC, notably in significantly improving chip manufacturing yield. As chip sizes increase to enhance performance, chip yield decreases due to the larger surface area. Chiplet technology can integrate various smaller chips with relatively high manufacturing yields, thus enhancing chip performance and yield.

Furthermore, Chiplet technology contributes to reduced design complexity and costs. Through heterogeneous integration, Chiplets can combine various types of small chips, reducing integration challenges in the initial design phase and facilitating design and testing. Additionally, since different Chiplets can be independently optimized, the final integrated product often achieves better overall performance.

Chiplets have the potential to lower wafer manufacturing costs. Apart from CPUs and GPUs, other units within chips can perform well without relying on advanced processes. Chiplets enable different functional small chips to use the most suitable manufacturing process, contributing to cost reduction.

With the evolution of semiconductor processes, chip design has become more challenging and complex, leading to rising design costs. In this context, Chiplet technology, which simplifies design and manufacturing processes, effectively enhances chip performance, and extends Moore’s Law, holds significant promise.

Applications and Development of Chiplets

In recent years, global semiconductor giants like AMD, TSMC, Intel, NVIDIA, and others have recognized the market potential in this field, intensively investing in Chiplet technology. For example, AMD’s recent products have benefited from the ‘SiP + Chiplet’ manufacturing approach. Moreover, Apple’s M1 Ultra chip achieved high performance through a customed UltraFusion packaging architecture. In academia, institutions like the University of California, Georgia Tech, and European research organizations have begun researching interconnect interfaces, packaging, and applications related to Chiplet technology.

In conclusion, due to Chiplet technology’s ability to lower design costs, reduce development time, enhance design flexibility and yield, while expanding chip functionality, it is an indispensable solution in the ongoing development of high-performance chips.

This article is from TechNews, a collaborative media partner of TrendForce.