SK hynix, as the market leader in HBM, targets to begin mass production of its GDDR7 chips in the fourth quarter of 2024, the company said on 13th June.

In the meantime, Micron also announced the launch of its GDDR7 graphics memory at Computex, which is currently being sampled. According to AnandTech, Micron not only plans to start mass production for GDDR7 this year, but also aims to do so early enough for some customers to ship finished products by year-end, with major applications range from AI and gaming to high-performance computing.

Samsung, on the other hand, is the first among the Big Three to present its GDDR7 products. According to its press release, Samsung has completed development of the industry’s first GDDR7 DRAM in July, 2023, a 16-gigabit  product, after its development of the industry’s first 24Gbps GDDR6 DRAM in 2022. According to AnandTech, Samsung is already sampling GDDR7 memory with the aim of launching it in 2024.

According to a report from AnandTech, SK hynix already has sample chips available for partners to test. Currently, the company plans to produce both 16Gbit and 24Gbit chips, with data transfer rates of up to 40 GT/s. As Samsung and Micron both expect to begin with 16Gbit chips running at 32 GT/s for their GDDR7 products, whether SK hynix could win customers’ favor by its faster speed attracts attention, AnandTech noted.

Read more

• [News] SK Hynix Reportedly Raises Prices Again, with DRAM Products to Increase by 15-20%
• [News] New Standard for DDR6 Memory to Come out Soon

(Photo credit: SK hynix)

As the standard DRAM market experiences an unprecedented cycle of supply-demand imbalance, the shortage of DDR3 production capacity has become even more severe.

According to a report from the Economic Daily News, with leading manufacturers like Samsung exiting DDR3 production, while demand for DDR3 from AI and edge computing devices continuing to increase, the storage capacity per single device is rising sharply. This is expected to drive a rebound in DDR3 prices, potentially benefiting related Taiwanese manufacturers such as Winbond, Elite Semiconductor Microelectronics Technology (ESMT), and Etron.

In response to the shift of operational focus to high-bandwidth memory (HBM) and DDR5, the world’s top three memory manufacturers are gradually phasing out the DDR3 market.

Reportedly, Samsung has informed customers that it will cease DDR3 production by the end of the second quarter. SK Hynix had already converted its DDR3 production at its Wuxi plant in China to DDR4 by the end of last year. Meanwhile, Micron has significantly reduced its DDR3 supply to expand its DDR5 and HBM production capacity.

As per industry sources cited in the same report, it’s said that as the reduction in production by major DRAM manufacturers continues to take effect, it has driven standard DRAM prices up from the second half of 2023 to the present, with further increases expected.

Thus, prices for niche memory like DDR3 tend to lag behind standard DRAM by one to two quarters. For Taiwanese manufacturers such as Winbond, ESMT, and Etron, which focus on DDR3, the benefits of DDR3 price increases will gradually become apparent this quarter and next.

The industry sources cited by the same report also point out that DDR3 applications remain quite widespread. For example, WiFi 6 devices predominantly uses DDR3, and the next generation, WiFi 7 devices, will still primarily use DDR3/DDR4. Additionally, edge computing devices would continue to adopt DDR3. With supply significantly decreasing while demand remaining strong, DDR3 prices are expected to continue their upward trend.

Read more

• [News] Controlled Market Demand Amid Earthquake Impact, Second Quarter DRAM Prices Expected to Rise by Over 20%
• [News] Increasing HBM Capacity to Sustain Market Share, SK Hynix Rumored to Upgrade Wuxi Plant

(Photo credit: Samsung)

According to the latest report by TheElec, though Samsung has been using thermal compression (TC) bonding until its 12-stack HBM, the company now confirms its belief that hybrid bonding is necessary for manufacturing 16-stack HBM.

Regarding its future HBM roadmap, Samsung reportedly plans to produce its HBM4 sample in 2025, which will mostly be 16 stacks, with mass production slated for 2026, the report noted. According to TheElec, earlier in April, Samsung used hybrid bonding equipment from its subsidiary, Semes, to produce a 16-stack HBM sample, of which it indicated to operate normally.

Citing information Samsung revealed during the 2024 IEEE 74th Electronic Components and Technology Conference last month, TheElec learned that Samsung considered hybrid bonding essential for HBM with 16 stacks and above.

According to the report, Samsung has been using thermal compression (TC) bonding until its 12-stack HBM. However, now it emphasized on hybrid bonding’s ability to reduce height, which would be indispensable for 16-stack HBM. By further narrowing the gap between chips, 17 chips (one base die and 16 core dies) can be fitted within a 775-micrometer form factor.

According to an earlier report from TechNews, Samsung and Micron use TC-NCF technology (thermal compression with non-conductive film) on HBM production, which requires high temperatures and high pressure to solidify materials before melting them, followed by cleaning. The industry has relied on traditional copper micro bumps as the interconnect scheme for packages, while their sizes pose challenges when trying to allow more chips to be stacked at a lower height.

Samsung stated that though making the core die as thin as possible or reducing the bump pitch could help, these methods have reached their limits. Sources cited by the Elec mentioned that it is very challenging to make the core die thinner than 30 micrometers. Also, using bumps to connect the chips has limitations due to the volume of the bumps. Thus, hybrid bonding technology may emerge as a promising solution.

While the current technology uses micro bump materials to connect DRAM modules, hybrid bonding, which could stack chips veritically by using through-silicon-via (TSV), can eliminate the need for micro bumps, significantly reducing chip thickness.

On the other hand, according to another report by Business Korea, SK hynix has shown its confidence in the HBM produced with Mass Reflow-Molded Underfill (MR-MUF) technology. MR-MUF technology attaches semiconductor chips to circuits, using EMC (liquid epoxy molding compound) to fill gaps between chips or between chips and bumps during stacking.

SK hynix reportedly plans to begin mass production of 16-layer HBM4 memory in 2026, and the memory heavyweight is currently researching hybrid bonding and MR-MUF for HBM4, but yield rates are not yet high, the report said.

Read more

• [News] The HBM4 Battle Begins! Memory Stacking Challenges Remain, Hybrid Bonding as the Key Breakthrough
• [News] Jensen Huang Confirms NVIDIA Approaches Certification of Samsung’s HBM Chips

(Photo credit: Samsung)

According to a report from TechNews, South Korean memory giant SK Hynix is participating in COMPUTEX 2024 for the first time, showcasing the latest HBM3e memory and MR-MUF technology (Mass Re-flow Molded Underfill), and revealing that hybrid bonding will play a crucial role in chip stacking.

MR-MUF technology attaches semiconductor chips to circuits, using EMC (liquid epoxy molding compound) to fill gaps between chips or between chips and bumps during stacking. Currently, MR-MUF technology enables tighter chip stacking, improving heat dissipation performance by 10%, energy efficiency by 10%, achieving a product capacity of 36GB, and allowing for the stacking of up to 12 layers.

In contrast, competitors like Samsung and Micron use TC-NCF technology (thermal compression with non-conductive film), which requires high temperatures and high pressure to solidify materials before melting them, followed by cleaning. This process involves more than 2-3 steps, whereas MR-MUF completes the process in one step without needing cleaning. As per SK Hynix, compared to NCF, MR-MUF has approximately twice the thermal conductivity, significantly impacting process speed and yield.

As the number of stacking layers increases, the HBM package thickness is limited to 775 micrometers (μm). Therefore, memory manufacturers must consider how to stack more layers within a certain height, which poses a significant challenge to current packaging technology. Hybrid bonding is likely to become one of the solutions.

The current technology uses micro bump materials to connect DRAM modules, but hybrid bonding can eliminate the need for micro bumps, significantly reducing chip thickness.

SK Hynix has revealed that in future chip stacking, bumps will be eliminated and special materials will be used to fill and connect the chips. This material, similar to a liquid or glue, will provide both heat dissipation and chip protection, resulting in a thinner overall chip stack.

SK Hynix plans to begin mass production of 16-layer HBM4 memory in 2026, using hybrid bonding to stack more DRAM layers. Kim Gwi-wook, head of SK Hynix’s advanced HBM technology team, noted that they are currently researching hybrid bonding and MR-MUF for HBM4, but yield rates are not yet high. If customers require products with more than 20 layers, due to thickness limitations, new processes might be necessary. However, at COMPUTEX, SK Hynix expressed optimism that hybrid bonding technology could potentially allow stacking of more than 20 layers without exceeding 775 micrometers.

Per a report from Korean media Maeil Business Newspaper, HBM4E is expected to be a 16-20 layer product, potentially debuting in 2028. SK Hynix plans to apply 10nm-class 1c DRAM in HBM4E for the first time, significantly increasing memory capacity.

Read more

• [News] Reasons for Samsung’s HBM Chips Failing Nvidia Tests Revealed, Reportedly Due to Heat and Power Consumption Issues
• [News] HBM Boom May Lead to DRAM Shortages in the Second Half of the Year

(Photo credit: SK Hynix)

JEDEC (the Solid State Technology Association) recently confirmed that the long-used SO-DIMM and DIMM memory standards will be replaced by CAMM2 for DDR6 (LPDDR6 included).

According to a report from WeChat account DRAMeXchange, the minimum frequency for DDR6 memory is 8800MHz, which can be increased to 17.6GHz, with a theoretical maximum of up to 21GHz, far surpassing that of DDR4 and DDR5 memory. CAMM2 is a brand new memory standard that also supports DDR6 standard memory, making it suitable for large PC devices like desktop PC. JEDEC expects to complete the preliminary draft of the DDR6 memory standard within this year, with the official version 1.0 expected by 2Q25 at the earliest, and specific products likely coming in 4Q25 or in 2026.

LPDDR6 will adopt a new 24-bit wide channel design, with a maximum memory bandwidth of up to 38.4GB/s, significantly higher than the existing LPDDR5 standard. The maximum rate for LPDDR6 can reach 14.4Gbps and the minimum rate is 10.667Gbps, matching the highest rate of LPDDR5x and far exceeding LPDDR5’s 6.7Gbps.

It is learned that a true CAMM2-standard LPDDR6, with a 32GB specification for example, costs about USD 500, which is five times the price of LPDDR5 (SO-DIMM/DIMM) memory.

Considering market adoption, the industry believes that the new CAMM2 standard adopted by DDR6 requires large-scale replacement of existing production equipment, which will bring about a new cost structure. Meanwhile, the evolution of new standards in the existing market will face high cost issue, which will restrict the large-scale adoption of DDR6 or LPDDR6.

Currently, upstream manufacturers like Samsung, SK Hynix, and Micron already have some memory products supporting the CAMM2 standard. Among downstream brand manufacturers, Lenovo and Dell also follow up and Dell reportedly has used CAMM2 memory boards in its enterprise product line in 2023.

Read more

• [News] LPDDR6’s Bandwidth Expected to be Increased over 100%

(Photo credit: Samsung)