HBM4, the sixth generation of HBM, is poised to become the key to breakthroughs in computing power for next-generation CSPs (Cloud Service Providers). According to a report from Commercial Times citing Global Unichip Corp. (GUC), to support the development of HBM4, their semiconductor IP (Intellectual Property) is already prepared and awaiting CSP manufacturers to advance their manufacturing processes.

GUC pointed out that if future clients need to integrate general-purpose HBM4 into ASICs (Application-Specific Integrated Circuits), GUC can provide assistance.

GUC further emphasized that its IP is ready for HBM4 development, waiting for CSPs to advance their manufacturing processes. Currently, the ASICs being mass-produced by CSPs still use HBM2 or HBM2e, while HBM3 is in the R&D stage.

The company candidly acknowledged that it cannot play any role at the moment and needs to wait for CSPs to adopt HBM4 on a large scale, taking cost considerations into account. When that time comes, GUC expects to assist CSPs in designing their solutions.

Currently, SK hynix has the technological capability for the general-purpose base die used in HBM4. However, when moving to more advanced processes like 5nm or beyond, external design service providers will be required.

Industry sources cited by Commercial Times believe that the pace of advancements in computing power is accelerating.

For instance, Google’s sixth-generation TPU, expected to be launched by the end of this year, is already based on TSMC’s 4nm process and designed on the Arm architecture.

Similarly, Meta’s upcoming MTIAv2 is built on TSMC’s 5nm process. The trend toward developing in-house chips is characterized by lower power consumption and larger memory capacities.

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(Photo credit: GUC)

Recently, Samsung Electronics announced that the development of its 8nm eMRAM has almost been completed and process upgrades is underway as planned.

According to a report from WeChat account DRAMeXchange, as a new type of non-volatile memory technology based on magnetic principles, eMRAM falls under the category of embedded MRAM (Magnetoresistive random-access memory). Compared to traditional DRAM, eMRAM offers faster access speeds and higher durability. Unlike DRAM, it does not require data refreshing, and its write rate is 1000 times that of NAND.

Due to these characteristics, the industry holds a positive outlook on the potential of eMRAM, especially in scenarios that demand high performance, energy efficiency, and durability.

Samsung Electronics is one of the main producers of eMRAM and is dedicated to promoting its adoption in the automotive sector. In 2019, Samsung developed and mass-produced the industry’s first eMRAM based on 28nm FD-SOI. After achieving the production capability of 28nm eMRAM, Samsung reportedly plans to mass-produce 14nm eMRAM in 2024, 8nm in 2026, and 5nm in 2027.

Samsung is confident about the application of eMRAM in future automotive uses, stating that its product’s temperature tolerance has reached 150-160°C, which can fully meet the stringent requirements of the automotive industry for semiconductors.

In recent years, the proliferation of big data and artificial intelligence applications has generated massive memory demands and placed higher requirements for memory technologies. Against this backdrop, new memory technologies have continuously emerged, among which SCM (Storage Class Memory) is a representative, which combines high-speed read and write performance of DRAM with the persistent storage capability of NAND flash, potentially addressing issues of small capacity, volatility, and high cost associated with DRAM. Key SCM products include phase-change memory (PCM), resistive RAM (ReRAM), magnetoresistive RAM (MRAM), and nanotube RAM (NRAM).

Aside from Samsung, companies like Kioxia and ByteDance have also acted vigorously in the new memory field this year. In April, Kioxia’s CTO Hidefumi Miyajima stated that compared to competitors developing both NAND and DRAM, Kioxia is at a competitive disadvantage in terms of business diversity, making the cultivation of new memory product business like SCM a necessity. With this goal in mind, Kioxia reorganized its “Memory Technology Research Laboratory” into the “Advanced Technology Research Laboratory.”

In March, it was reported by South China Morning Post that ByteDance invested in a Chinese memory company Innostar, becoming its third-largest shareholder. Innostar focuses on the R&D of new memory technologies like ReRAM and related chip products covering three categories: high-performance industrial control/automotive-grade SoC/ASIC chip, computing-in-memory (CIM) IP, chip and system-on-memory (SoM) chip.

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• [News] Intel’s Lunar Lake Bundled Memory Reportedly Causes Uproar in the PC Supply Chain
• [News] Battle in AI PCs: Exploring Intel, AMD, and Qualcomm Chips’ AI Computing Power

(Photo credit: Samsung)

Driven by the AI chip wave, “advanced packaging” emerges as the hottest technology in the semiconductor industry. Its significance extends beyond computational power demands, as the escalating cost of semiconductor processes and the limits of Moore’s Law make the “integration capability” of advanced packaging a crucial weapon for industry players to break through.

According to a report from TechNews, TSMC, Intel, and Samsung have all been deeply involved in advanced packaging for many years and have already introduced corresponding solutions. However, these semiconductor giants are not only focused on this aspect.

In addition to their own technologies, they are actively fostering supply chains, setting standards, and building ecosystems. By accelerating the development of advanced packaging technology, they are also laying the groundwork for their future influence.

Intel, for instance, has chosen to start with standardization by proposing the Universal Chiplet Interconnect Express (UCIe) alliance. Through open specifications and standardized connections, the protocol directly adopts mature standards like PCI Express (PCIe) and the recently developed Compute Express Link (CXL).

The reason for starting with chiplet technology is that in recent years, more and more semiconductor companies have discovered that designing chips using Chiplet architecture and integrating them through advanced packaging technology is more cost-effective than traditional System-on-Chip (SoC) approaches.

Therefore, Intel’s focus on connecting chiplets through standards like UCIe is aimed at providing a standardized interface stack for complete chiplet integration. UCIe supports 2D, 2.5D, and bridge packaging, with future development expected to include support for 3D packaging as well.

Intel’s Packaging Test Technology Development Department’s Senior Chief Engineer, Zhiguo Qian, directly involved in the UCIe Alliance, emphasizes that advanced packaging has become a crucial aspect of semiconductor development, particularly in ensuring the continuation of Moore’s Law.

Qian further points out that when considering the impact of the UCIe standard on the advanced packaging industry, it indeed establishes a standard for interconnecting chiplets within SoCs. This was the original intent behind Intel’s promotion of the UCIe standard alliance.

Currently, advanced packaging is mostly divided into different structures like 2.5D and 3D, and some even classify it as 2.1D or 2.2D, showcasing diverse structural designs across the industry.

However, within these structures, each company has its own proprietary interface solutions, and some even offer multiple solutions. Therefore, to meet customer demands, these standard interconnections must not only be at the forefront of technology but also be compatible with various standards that are open and do not incur any licensing fees.

On the other hand, the UCIe alliance has established various standards, such as the required packaging architectures and interface wiring designs, to achieve the desired performance levels. These standards provide guidelines for customers seeking advanced packaging solutions. By adhering to UCIe standards, customers can anticipate the performance of their chips, without the need for trial and error(in the IC designing stage).

Source: Intel

Currently, companies participating in the UCIe alliance include Qualcomm, AMD, Arm, NVIDIA, TSMC, ASE Group, Winbond Electronics, and Applied Materials, among others, along with semiconductor giants like Samsung. Additionally, Google Cloud, Microsoft, and Meta are members, alongside over 120 other companies.

• TSMC Propels 3D Fabric Alliance

TSMC is also focused on ecosystem development, as evidenced by its announcement of the 3DFabric Alliance within the Open Innovation Platform (OIP) during the 2022 Open Innovation Platform Ecosystem Forum.

In fact, the 3DFabric Alliance is built upon TSMC’s 3DFabric technology introduced in 2020. This technology encompasses a comprehensive solution ranging from advanced processes to silicon stacking and advanced packaging technologies such as CoWoS and InFO.

With an established customer base for its 3DFabric technology, TSMC expanded it into an alliance in 2022. The goal is to assist customers in achieving rapid implementation of chip and system-level innovations while strengthening TSMC’s influence in advanced packaging.

The 3DFabric Alliance marks TSMC’s sixth open innovation platform alliance and is the semiconductor industry’s first alliance aimed at accelerating innovation and enhancing the 3D Integrated Circuit (3D IC) ecosystem in collaboration with partners.

This alliance includes companies in electronic design automation (EDA), silicon intellectual property (IP), design center alliances (DCA)/value chain alliances (VCA), memory, outsourced packaging testing (OSAT), and substrate and testing. Members include Ansys, Cadence, Siemens, ARM, Micron, Samsung, SK Hynix, Amkor, ASE, Advantest, and more.

Source: TSMC

In addition to establishing the alliance, TSMC also introduced the 3Dblox standard during the alliance’s inception. This standard integrates the design ecosystem with validated EDA tools and processes to support 3DFabric technology.

The purpose of this standard is to break the complexity of 3D IC design caused by each EDA supplier using its preferred language. Through the modular 3Dblox standard, key physical stacking and logic connection information in 3D IC design are standardized in a single format, simplifying input and significantly enhancing interoperability among different tools in 3D IC design.

From Intel’s UCIe standard to TSMC’s 3DFabric alliance and 3Dblox standard, it’s evident that in the era of advanced packaging, the key to solidifying the positions and market shares of semiconductor giants lies not only in their individual technological breakthroughs but also in their ability to coordinate and integrate the upstream and downstream industries.

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• [News] The Era of Heterogeneous Integration Approaches: Who Shall Dominate the Advanced Packaging Field?

(Photo credit: TSMC)

The semiconductor industry enters the era of integration. Various foundries are focusing on advanced packaging technologies, but the terminology surrounding advanced packaging can be daunting. This article aims to explain these terms in the simplest way possible.

According to a report from TechNews, currently, there are two main trends in advanced packaging: heterogeneous integration and chiplets.

In fact, the concept of “heterogeneous integration” has been developing for many years and is not exclusive to advanced packaging. It is not only used for the integration of heterogeneous chiplets but also for integrating other non-chip active/passive components into a single package, which is the technology commonly used in traditional Outsourced Semiconductor Assembly and Test Services(OSATs).

• Heterogeneous Integration = Big Building Blocks? Advanced Packaging = Small Building Blocks? 

In the simplest terms, “heterogeneous integration” can be likened to building with large building blocks, while “advanced packaging” is akin to assembling with small building blocks. Some manufacturers, like traditional Outsourced Semiconductor Assembly and Test Services(OSATs), excel in stacking large blocks, such as logic circuits, radio frequency circuits, MEMS (Micro-Electro-Mechanical Systems), or sensors, onto a IC substrate. The stacking of these different large blocks represents the concept of heterogeneous integration.

On the other hand, some blocks are too small to stack effectively, requiring assistance from advanced packaging, typically provided by semiconductor foundries.

Advanced packaging also encompasses 2.5D packaging and 3D packaging. Using the metaphor of building blocks, the former involves horizontally stacking small building blocks on a interposer, while the latter involves vertically stacking small building blocks with interconnection facilitated through Through-Silicon Vias (TSVs), which are ultra-small building blocks.

It’s important to emphasize that stacking blocks is a conceptual representation, and the distinction between large and small blocks is relative. The analogy above refers to heterogeneous integration in traditional packaging, and heterogeneous integration in advanced packaging follows a similar concept, but with even smaller building blocks.

• SoC / SiP / Heterogeneous Integration / Chiplet

With this concept in mind, let’s discuss the applications of heterogeneous integration in advanced packaging:

Among the various packaging types, SoC (System On Chip) involves integrating different chips such as processors and memory, with different functions, redesigned and fabricated using the “same process,” integrated onto a single chip, resulting in a final product with only one chip.

On the other hand, SiP (System in Package) involves connecting multiple chips with “different processes” through “heterogeneous integration” technology, integrated within the same packaging module. Therefore, the final product will be a system with many chips on it, resembling the stacking of different-sized building blocks mentioned earlier.

Therefore, heterogeneous integration refers to integrating different and separately manufactured components (heterogeneous) into higher-level assemblies. These components include blocks of different sizes, such as MEMS devices, passive components, logic chips, and more.

However, at a certain point, for the sake of process development, researchers found that separating components at the right time might facilitate miniaturization. Hence, chiplet was born.

• Is Chiplet the Fusion of Heterogeneous Integration and Advanced Processes?

As demands for ICs become increasingly complex, the size of SoC chips continues to grow. However, cramming too many components onto a limited substrate poses significant challenges, including heightened process complexity and reduced yield.

Hence, the concept of chiplets emerged, advocating for the segmentation of SoC functionalities, such as data storage, computation, signal processing, and data flow management, into smaller individual chips. These chiplets are then integrated through packaging to form a interconnected network.

It’s worth noting that Chiplets are essentially chips, whereas SiP refers to the packaging format. Chiplet architecture enable the reduction of individual chip sizes, simplify circuit design, overcome manufacturing difficulties and yield issues, and offer greater design flexibility.

• Advanced Packaging Technologies in Foundries

Currently, advanced packaging can be broadly categorized into three main types: Wafer-Level Packaging (WLP), 2.5D Packaging, and 3D Packaging. Traditional packaging involves cutting wafers into chips before packaging, while advanced packaging entails packaging the silicon wafer before cutting, requiring subsequent stacking processes in fabs. Therefore, the technology is primarily the responsibility of fabs.

Traditional packaging involves cutting wafers into chips before packaging. Advanced packaging, starting from wafer-level packaging, involves packaging silicon wafers before cutting, and subsequent stacking requires wafer fabrication processes.

Therefore, this article will delve into advanced packaging technologies offered by the three major foundries, with a focus on 2.5D and 3D packaging.

• 2.5DIC / 3DIC Packaging

To further explain using building blocks, the difference between 2.5D and 3DIC packaging lies in the “stacking method.”

In 2.5D packaging, processors, memory, or other chips are stacked horizontally on a silicon interposer using a flip-chip method, with micro bumps connecting different chip’s electronic signals. Through silicon vias (TSVs) in the interposer link to the metal bumps below, then packaged onto the IC substrate, creating tighter interconnections between the chips and the substrate.

In a side view, although the chips are stacked, the essence remains horizontal packaging, with the chips positioned closer together and allowing for smaller chip sizes. Additionally, this is a form of “heterogeneous integration” technology.

3D packaging involves stacking multiple chips (face down) together, directly using through-silicon vias to stack them vertically, linking the electronic signals of different chips above and below, achieving true vertical packaging. Currently, more and more CPUs, GPUs, and memories are starting to adopt 3D packaging technology.

• Hybrid Bonding

Hybrid bonding is one of the die bonding techniques used in advanced chip packaging processes. One of the commercially available technologies in this domain is the “Cu-Cu hybrid bonding.”

In traditional wafer bonding processes, there are interfaces between copper and dielectric materials. With “Cu-Cu hybrid bonding,” metal contacts are embedded within the dielectric material. Through a thermal treatment process, these two materials are bonded together, utilizing the atomic diffusion of copper metal in its solid-state to achieve the bond. This approach addresses challenges encountered in previous flip-chip bonding process.

Compared to flip-chip bonding, hybrid bonding offers several advantages. It allows for achieving ultra-high I/O counts and longer interconnect lengths. By using dielectric material for bonding instead of bottom fillers, the cost of filling is eliminated.

Additionally, hybrid bonding results in minimal thickness compared to chip-on-wafer bonding. This is particularly beneficial for future developments in 3D packaging, where stacking multiple layers of chips is required, as hybrid bonding can significantly reduce the overall thickness.

• Advanced Packaging Moves Towards the Era of Heterogeneous Integration

As the semiconductor industry enters the “post-Moore’s Law era,” the development focus of advanced packaging is gradually shifting from 2D planar structures to 3D stacking and from single-chip designs to multi-chip configurations. Therefore, “heterogeneous integration” will play a crucial role in future advanced packaging.

Currently, prominent companies such as TSMC, Samsung, and Intel are intensifying their research and development efforts and capacity expansions in this field, introducing their innovative packaging solutions.

With ongoing technological advancements and innovations, advanced packaging and heterogeneous integration will play increasingly vital roles in propelling the semiconductor industry towards greater heights, meeting the complex and diverse demands of future electronic devices.

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• [News] The Era of Heterogeneous Integration Approaches: Who Shall Dominate the Advanced Packaging Field?

(Photo credit: Intel)

Novatek has unveiled its AI and related domain strategies during its year-end investor conference. According to a report from Taiwanese news outlet Tai Sounds, Novatek anticipates that the demand for AI will drive an enhancement in display specifications and necessitate the integration of edge devices such as security systems.

Transmission interfaces stand as the core focus of Novatek, with subsequent products extending towards high-speed transmission. In both its driver IC and SoC product lines, Novatek maintains customized product lines, with expectations for growth in customized chips this year.

As per sources cited by Taiwanese news outlet Tai Sounds, Novatek is rumored to be venturing into the IP domain and may have opportunities to collaborate with ARM, a subsidiary of SoftBank Group.

Further clarification from the source also indicates that Novatek specializes in customized power management chips for mobile devices, while Realtek offers USB4 hub solutions.

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(Photo credit: Novatek)