Although current semiconductor process technologies have evolved to the 3nm and 5nm nodes, SoC (system on a chip) architecture has yet to be manufactured at these nodes, as memory and RF front-end chiplets are yet to reach sufficient advancements in transistor gate length and data transmission performance. Fortunately, EDA companies are now attempting to leverage heterogeneous integration packaging technologies to link the upstream and downstream semiconductor supply chains as well as various IP cores. Thanks to this effort, advanced packaging technologies, including 2.5D/3D IC and SiP, will likely continue to push the limits of Moore’s Law.

While SoC development has encountered bottlenecks, EDA tools are the key to heterogeneous integration packaging

As semiconductor process technologies continue to evolve, the gate length of transistors have also progressed from μm (micrometer) nodes to nm (nanometer) nodes. However, the more advanced process technologies are not suited for manufacturing all semiconductor components, meaning the development of SoC architectures has been limited as a result. For instance, due to physical limitations, memory products such as DRAM and SRAM are mostly manufactured at the 16nm node at the moment. In addition, RF front-end chiplets, such as modems, PA (power amplifiers), and LNA (low noise amplifiers) are also primarily manufactured at the 16nm node or other μm nodes in consideration of their required stability with respect to signal reception/transmission.

On the whole, the aforementioned memory, and other semiconductor components cannot be easily manufactured with the same process technologies as those used for high-end processors (which are manufactured at the 5nm and 3nm nodes, among others). Hence, as the current crop of SoCs is not yet manufactured with advanced processes, EDA companies including Cadence, Synopsys, and Siemens (formerly Mentor) have released their own heterogeneous integration packaging technologies, such as 2.5D/3D IC and SiP (system in package), in order to address the demand for high-end AI, SoC architecture, HPC (high performance computing), and optical communication applications.

EDA companies drive forward heterogeneous integration packaging as core packaging architecture and integrate upstream/downstream supply chain

Although the current crop of high-end semiconductor process technologies is still incapable of integrating such components as memory, RF front-end, and processors through an SoC architecture, as EDA companies continue to adopt heterogeneous integration packaging technology, advanced packaging technologies, including 2.5D/3D IC and SiP, will likely extend the developmental limitations of Moore’s Law.

Information presented during Semicon Taiwan 2021 shows that EDA companies are basing their heterogeneous integration strategies mainly on the connection between upstream and downstream parts of the semiconductor supply chain, in addition to meeting their goals through chip packaging architectures. At the moment, significant breakthroughs in packaging technology design and architecture remain unfeasible through architectural improvements exclusively. Instead, companies must integrate their upstream chip design and power output with downstream substrate signal transmission and heat dissipation, as well as other factors such as system software and use case planning. Only by integrating the above factors and performing the necessary data analysis can EDA companies gradually evolve towards an optimal packaging architecture and in turn bridge the gap of SoC architectures.

With regards to automobiles (including ICE vehicles and EVs), their autonomous driving systems, electronic systems, and infotainment systems require numerous and diverse semiconductor key components that range from high-end computing chips to mid-range and entry-level MCUs. As such, automotive chip design companies must carefully evaluate their entire supply chain in designing automotive chip packages, from upstream manufacturers to downstream suppliers of substrates and system software, while also keeping a holistic perspective of various use cases. Only by taking these factors into account will chip design companies be able to respond the demands of the market with the appropriate package architectures．

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