Taiwan’s semiconductor manufacturing is making strides in advanced process and packaging expansion. TSMC’s new 2nm fab in Kaohsiung will hold a tool-in ceremony this November, followed by equipment installations in December. Meanwhile, ASE’s Siliconware Precision Industries is set to expand advanced packaging capacity in the Erlin Science Park.

According to the Liberty Times, TSMC’s first 2nm fab in Kaohsiung’s Nanzih District is nearing completion. Industry sources indicate that TSMC has scheduled a low-profile tool-in ceremony with equipment suppliers on November 26, led by COO Y.P. Chyn, with equipment installations to begin on December 1. The Nanzih site is expected to serve as TSMC’s primary base for 2nm production.

The report also highlights the rapid progress at TSMC’s Nanzih facility. The P1 fab is nearing completion, with the office tower and P2 fab structure already in place, while groundbreaking for a third fab (P3) occurred this month. Industry insiders note that a fourth and fifth fab (P4 and P5) have received environmental approvals and could serve as wafer production sites for TSMC’s A16 process under the 2nm generation.

Key equipment suppliers, including Lam Research, ASML, and Tokyo Electron, have begun establishing presences in Kaohsiung to support this next-generation fab.

In related developments, ASE Technology announced on October 28 that its subsidiary Siliconware Precision Industries will invest NTD 419 million to secure land-use rights in the Erlin Science Park. According to a report from the Commercial Times, industry sources indicate this acquisition is primarily to expand CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging capacity.

TSMC CEO C.C. Wei noted earlier in its third quarter earnings call that CoWoS advanced packaging capacity remains constrained. TSMC has committed to doubling CoWoS capacity by year-end and will continue expanding in 2025 to better align supply with demand. However, due to ongoing capacity limitations, the Commercial Times reported that TSMC stated the capacity shortfall had led them to expand outsourcing to OASTs, seeking support from industry partners.

(Photo credit: TSMC)

The surging global demand for AI chips is straining advanced packaging capacity, driving a sharp focus on fan-out panel-level packaging (FOPLP) within Taiwan’s semiconductor industry. According to a report by Commercial Times, major packaging and testing firms such as ASE and Powertech, alongside equipment manufacturers like Gudeng, GPTC, E&R Engineering, Mirle, and analysis firm MAtek, are investing heavily in FOPLP technology.

The rapid development and expanding applications of AI chips have intensified the need for higher chip performance, smaller sizes, better heat dissipation, and lower costs. As emerging applications such as 5G, AIoT, and automotive chips continue to grow, the demand for high-performance, high-power semiconductors has surged. FOPLP technology, which enhances performance while significantly cutting costs and addressing thermal and signal integration issues, is emerging as a key trend in the market.

ASE has been working on panel-level packaging for several years. The company expects its panel-level packaging equipment to be in place by the second quarter of 2025, maintaining a technological edge. On October 2, ASE announced a nearly NT$8 billion purchase of equipment by its subsidiary, SPIL, from companies including Advantest.

Powertech has already moved into wafer-level fan-out packaging and is now shifting toward panel-level fan-out packaging. The company claims that the new technology can increase chip area output by two to three times. It has dedicated its Hsinchu plant to panel-level fan-out packaging and TSV CIS, positioning itself for future growth opportunities.

Equipment manufacturers are also seeking to capitalize on this trend. GPTC, a supplier to major foundries for InFO packaging, is expected to benefit from future FOPLP opportunities due to the similar nature of its equipment. Gudeng Precision is developing panel-level packaging transport boxes, with mass production expected in 2025.

FOPLP combined with TGV drilling is seen as the key to this technology. Analysts cited by Commercial Times highlight that FOPLP+TGV enables higher area utilization and unit capacity, which effectively reduces heterogeneous packaging costs.

E&R Engineering is focusing on drilling, testing, and cutting equipment for glass substrates, primarily supplying panel manufacturers in Taiwan and outsourced assembly and testing providers in Southeast Asia. Mirle has targeted glass substrate transport equipment, while MAtek is leading the market in glass substrate inspection technology.

(Photo credit: ASE)

ACM Research, Inc., a provider of wafer processing solutions for semiconductor and advanced wafer-level packaging applications in China, announced on September 3rd the release of its Ultra C bev-p panel bevel etching tool for fan-out panel-level packaging (FOPLP) applications.

This new tool is designed for bevel etching and cleaning in copper-related processes, offering dual-side bevel etching for both the front and back of panels within a single system, further boosting process efficiency and enhances product reliability.

Moreover, a day after the announcement, the company further revealed that it had received purchase orders for four wafer-level packaging tools, including two from a U.S.-based customer and two from a U.S.-based research and development (R&D) center.

Dr. David Wang, ACM’s president and chief executive officer, believes that FOPLP will grow in importance as it addresses the evolving needs of modern electronic applications, offering benefits in integration density, cost efficiency, and design flexibility.

Reportedly, the new Ultra C bev-p tool is designed to deliver advanced performance, utilizing ACM’s expertise in wet processing. It is one of the first tools to incorporate double-sided bevel etching for horizontal panel applications.

Together with the Ultra ECP ap-p for electrochemical plating and the Ultra C vac-p flux cleaning tools, the Ultra C bev-p is expected to support the FOPLP market by enabling advanced packaging on large panels with high-precision features.

ACM emphasizes that the Ultra C bev-p tool is a critical enabler for FOPLP processes, employing a wet etching technique tailored for bevel etching and copper residue removal.

This process plays a vital role in preventing electrical shorts, reducing contamination risks, and preserving the integrity of subsequent processing steps, ensuring long-term device reliability. The tool’s effectiveness is driven by ACM’s patented technology, designed to tackle the specific challenges of square panel substrates.

Different from traditional round wafers, ACM’s design is said to ensure precise bevel removal process that stays confined to the bevel region, even on warped panels. This is essential for maintaining the integrity of the etching process while ensuring the high performance and reliability needed for advanced semiconductor technologies.

Currently, major players in the FOPLP advanced packaging field include Powertech Technology, ASE Group, SPIL, TSMC, Innolux, JSnepes, and Samsung Electro-Mechanics.

TrendForce points out that FOPLP technology presents advantages and disadvantages. Its main strengths are lower unit cost and larger package size, but as its technology and equipment systems are still developing, the commercialization process is highly uncertain.

It is estimated that the mass production timeline for FOPLP in consumer IC and AI GPU may fall between the second half of 2024 to 2026, and 2027-2028, respectively.

Read more

• [News] ACM Research Steps into FOPLP Advanced Packaging Field
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(Photo credit: ACMR)

Despite recent issues with NVIDIA’s GB200 shipments, the market remains optimistic about long-term AI demand, and CoWoS capacity continues to be in short supply.

According to a report from MoneyDJ, TSMC will assign orders of the initial stage of chip stacking in CoWoS packaging, Chip on Wafer (CoW), for the first time, to semiconductor assembly and test service provider SPIL.

The process will reportedly to manufactured at SPIL’s Zhong Ke Facility in Taichung. The company is said to build new capacity, with tool-in expected in the second quarter of 2025 and production ramping up in the third quarter.

TSMC President C.C. Wei previously disclosed that this year’s CoWoS capacity will more than double, with the growth trajectory similar in 2025. The company will continue to collaborate with OSATs to advance their packaging capabilities, Wei said.

Tien Wu, COO of another major outsourced semiconductor assembly & test services (OSAT) company ASE, also mentioned at its recent earnings call that the company has been co-developing both oS and CoW processes with their foundry partners for many years.

In fact, CoWoS is already a well-established technology. TSMC has been outsourcing the WoS (Wafer-on-Substrate) process, targeting small-batch, high-performance chips, while retaining the high-margin, high-tech CoW process in-house.

Lower-margin oS processes are handed over to packaging and testing companies. During the initial phase of this expansion wave, TSMC did not release CoW orders, but due to the overwhelming demand, they now have to outsource part of the process.

Industry sources cited by MoneyDJ further reveal that even Chinese companies have been excluded from the list, there are still several OSATs capable of handling TSMC’s outsourced CoWoS processes, such as Amkor, ASE, and SPIL.

After evaluation, SPIL’s plant in Central Taiwan was selected. It is reported that SPIL already collaborates with NVIDIA and AMD in the advanced packaging field, possessing capabilities not only for CoWoS-S but also for the higher-end CoWoS-L. This makes SPIL a strong second supplier for these major American companies.

Reportedly, TSMC will release the first phase of CoWoS-S orders to SPIL. Currently, SPIL’s CoWoS-related capacity is about 40,000 to 50,000 wafers per year. They plan to tool-in at the plant in Central Taiwan Science Park around the second quarter of next year.

It’s estimated by MoneyDJ’s report that TSMC’s CoWoS capacity remains in short supply, at 35,000 to 40,000 wafers per month this year. With the additional outsourced capacity, next year’s production could reach over 65,000 wafers per month, or possibly higher.

Read more

• [News] TSMC Rumored to Build New CoWoS Plant in Southern Taiwan
• [News] CoWoS Booming, TSMC Price Hikes Reportedly Imminent

(Photo credit: TSMC)

“It is not the shortage of AI chips, it is the shortage of our CoWoS capacity,” replied TSMC Chairman Mark Liu during an interview in September last year, propelling this technology that TSMC had quietly cultivated for over a decade into a global spotlight.

As per a report from TechNews, the hardware demand sparked by generative AI has also led to “advanced packaging” becoming not only a hot keyword pursued by global investors but also a prominent feature of the semiconductor industry. From foundries and memory manufacturers to OASTs, all are actively involved in the research and capacity expansion of advanced packaging technologies.

TSMC, the leading force in the advanced packaging market, has repeatedly emphasized its efforts to expand capacity during its earnings call, including capacity expansions in Zhunan and Hsinchu, and even the possibility of constructing advanced packaging facilities in Chiayi.

Intel’s strategic moves also underscore its emphasis on the development of advanced packaging. Intel’s new plant completed in Penang, Malaysia in 2023 is aimed at establishing advanced packaging capacity.

Leading packaging and testing company, ASE Technology Holding, has also actively participated in the competition for advanced packaging. Apart from its subsidiary, Siliconware Precision Industries (SPIL), which is already a supplier for the backend packaging of CoWoS, ASE Technology Holding is also expanding advanced packaging capacity at its facility in Kaohsiung.

Memory manufacturers are also aggressively ramping up their advanced packaging capacity. SK Hynix, which exclusively supplies HBM for NVIDIA AI chips, recently announced plans to invest USD 1 billion in the development of advanced packaging. They view advanced packaging as the “future focus of semiconductor development for the next 50 years.

Advanced Packaging: Over a Decade of Development

In fact, advanced packaging is not a new concept. Tracing the history of packaging technology, the year 2000 undoubtedly marked a turning point. From this year onwards, packaging technology shifted from traditional wire bonding and flip-chip methods to “wafer-level packaging,” where most or all packaging and testing processes are conducted on the wafer itself.

The 2.5D packaging, which gained significant attention after 2023, actually emerged as early as 2010. However, due to cost concerns, the number of manufacturers adopting this technology was relatively limited, with a focus on high-performance computing chips.

Chiang Shang-yi, the Chief Strategy Officer of Foxconn Semiconductor, recalled the initial lack of interest in CoWoS technology, which even led to him being regarded as a “joke” within the company( TSMC) for proposing advanced packaging. He also revealed that the first company willing to adopt the costly CoWoS technology was actually Huawei.

▲ Semiconductor Packaging Technology Evolution compiled by McKinsey, Accelerated Technological Evolution after 2000 (Source: McKinsey)

Compared to 2D packaging technology, 2.5D packaging involves placing an intermediate layer between the chip and the IC substrate and stacking different chips in parallel. TSMC’s CoWoS has become synonymous with 2.5D packaging, where a silicon interposer layer is inserted between the chip and the SiP substrate, and metal layers are connected using Through-Silicon Vias (TSVs) to overcome the density limitations of SiP substrates, which previously restricted the number of chips.

Despite TSMC’s dominance, Intel, with its extensive technical expertise in CPU packaging, cannot be underestimated. In the 2.5D packaging battlefield, Intel employs EMIB technology as its strategy. Unlike CoWoS, EMIB does not utilize a silicon interposer layer.

Instead, its key feature lies in the “Silicon Bridge,” buried within the packaging substrate, which connects the bare dies. Intel believes that EMIB offers cost advantages compared to solutions using large silicon interposer layers.

In recent years, Samsung, which has been actively cultivating the semiconductor foundry market, has also ventured into the 2.5D packaging arena. Their proprietary I-Cube technology has traditionally targeted applications in High-Performance Computing (HPC) chips. When Samsung introduced I-Cube4 in 2021, it emphasized the integration of multiple logic dies and HBM placed on a silicon interposer layer, enabling heterogeneous integration into a single chip.

As Moore’s Law approaches its limits and the massive computational demands triggered by generative AI continue to surge, coupled with the trend towards lighter, thinner, and smaller end products, chips are inevitably evolving towards more transistors, greater computational power, and lower power consumption performance.

Therefore, the transition of packaging technology from 2.5D to 3D is undoubtedly an inevitable development.

The difference between 3D and 2.5D packaging lies in the stacking method. In 2.5D packaging, chips are stacked parallelly on an intermediate layer, while in 3D packaging, chips are stacked vertically in a three-dimensional manner.

The advantage of 3D packaging lies in its ability to create more space for transistors within a chip through stacking, shorten the distance between different bare dies significantly, enhance transmission efficiency, and reduce power consumption during transmission.

TSMC, Intel, and Samsung Racing for 3D Packaging Technology

TSMC’s positioning in 3D IC technology is undeniable. Its SoIC technology adopts the wafer-to-wafer bonding technique. SoIC integrates homogeneous and heterogeneous small dies into a single chip, with smaller dimensions and a thinner profile. It can be integrated into 2.5D CoWoS or InFO. From an external perspective, SoIC resembles a universal SoC chip but integrates various functions heterogeneously.

Intel’s layout in 3D packaging revolves around its 3D Foveros technology. Structurally, the bottom layer comprises a packaging substrate, with a bottom wafer placed on top serving as an intermediate layer. Within this intermediate layer, numerous TSVs (Through-Silicon Vias) are present, facilitating connections between the upper chips, modules, and other parts of the system to achieve transmission purposes.

Samsung’s X-Cube 3D packaging technology utilizes TSV processes. Currently, Samsung’s X-Cube test chips can stack the SRAM layer on top of the logic layer, interconnected via TSVs, employing its 7nm EUV process technology.

TSMC’s Comprehensive Ecosystem Strategy

Currently dominating the advanced packaging market, thanks to its acquisition of large contracts for manufacturing NVIDIA AI chips, TSMC is not only continuing to develop more advanced packaging technologies but is also actively promoting its 3D Fabric platform.

In addition to incorporating the three key packaging technologies CoWoS, InFo, and SoIC, this platform has expanded into an industry alliance. It includes participation from EDA, IP, DCA/VCA, memory, packaging and testing suppliers, as well as substrate and testing vendors. The goal is to create a complete 3D Fabric ecosystem, strengthen innovation, and enhance customer adoption willingness.

This alliance has attracted active participation from heavyweight players in the semiconductor upstream supply chain. Even companies traditionally seen as competitors in the packaging and testing sector, such as Amkor, ASE Technology Holding, and Siliconware Precision Industries (SPIL), are members. The comprehensive supply chain has become a significant advantage for TSMC in providing advanced packaging contract manufacturing services.

▲ TSMC’s 3D Fabric Alliance members, including major players from EDA to packaging and testing companies. (Image Source: TSMC)

In comparison, Intel, despite its robust technological expertise developed over many years and its proposition to independently provide wafer manufacturing or testing services, faces a disadvantage in expanding its market share in advanced packaging due to its lack of experience in the foundry market.

On the other hand, Samsung, compared to TSMC, is constrained by its yield issues in advanced processes. This limitation leads IC design companies to prioritize foundries with more stable yields when considering outsourcing comprehensive manufacturing services.

Read more

• [News] SK Hynix Reportedly Invests USD 1 Billion in Advanced Packaging to Strengthen HBM Chip Leadership
• [News] TSMC Reportedly Doubles CoWoS Capacity while Amkor, ASE also Enter Advanced Packaging for AI

(Photo credit: TSMC)