According to a report from Wccftech, Google is rumored to switch to TSMC’s second-generation 3nm process, “N3E”, for its Tensor G5. The report also claims that for the Tensor G6, Google will utilize TSMC’s “N3P” process instead of the 2nm process speculated earlier. Its entire Pixel 10 series set to be launched next year will use TSMC’s 3nm process.

The report suggests that the Tensor G4 processor may be the last Google chipset manufactured by Samsung using its 4nm process, since the Tensor G4 reportedly offers only a slight upgrade compared to the Tensor G3 in the Pixel 8 smartphone, as it continues to use Samsung’s older FO-PLP packaging technology instead of the newer FO-WLP packaging, which is more capable in preventing overheating.

Notably, the report states that Qualcomm and MediaTek have also adopted the 3nm “N3E” process for their Snapdragon 8 Elite and Dimensity 9400 chipsets for the first time this year, having bridged the technological gap with Apple.

Therefore, the report notes that Google will still be a year behind in the competition when it announces the Tensor G5 and Tensor G6, since Qualcomm, MediaTek, and Apple are already using TSMC’s 3nm process and are expected to shift to N3P.

According to the report, the Tensor G5 was reported to have reached the tape-out stage earlier this year and is expected to use TSMC’s InFO-POP packaging, which allows the chipset’s packaging to be smaller and also more power efficient.

Regarding Tensor G6, it will likely launch two years from now. Although it was previously rumored that Tensor G6 will use TSMC’s 2nm process, the report indicates that it will instead utilize TSMC’s enhanced version of 3nm, N3P node.

According to a report from AnandTech, as a more enhanced process node compared to N3E, N3P offers better performance with higher transistor density and reduced power consumption.

The report indicates that it makes sense that Google is not opting to adopt the 2nm process immediately, especially since even Apple is expected to wait until the launch of the iPhone 18, two years from now, to introduce its first A-series chipsets that will exceed the 3nm barrier. Additionally, it is expected that the 2nm A-series chipsets will not be included in all iPhone 18 models due to their high cost.

Read more

• [News] TSMC Rumored to Secure Tensor G6 Orders from Google with Its 2nm Process
• [News] Google’s Tensor G5 Reportedly Manufactured with TSMC’s 3nm and InFO-POP Packaging

(Photo credit: Google)

On September 9, Indian tech blog PiunikaWeb cited a report from Tech & Leaks Zone, stating that rumors have hinting at Google’s preparation to exit Samsung Electronics’ wafer foundry business, Samsung Foundry, and switch to TSMC in 2025. The next two generations of Google’s custom Tensor processors are reportedly expected to use TSMC’s 3nm and 2nm processes, respectively.

As per the same report, Google’s Tensor G4 processor is being manufactured by Samsung Foundry using its 4nm process. However, the G4 offers only a slight upgrade compared to the Tensor G3 in the Pixel 8 smartphone, as the G4 continues to use Samsung’s older FO-PLP packaging technology instead of the newer FO-WLP packaging, which is more capable in preventing overheating.

On the other hand, Google’s Tensor G5, which will be used in the Pixel 10, is reportedly set to be manufactured by TSMC using the latest 3nm process and TSMC’s advanced InFO-POP packaging technology. The Tensor G6, which will support the Pixel 11 series, will also be produced by TSMC using 2nm process.

Notably, Apple had introduced an AI technical document in June, disclosed that two AI models supporting “Apple Intelligence” were trained in the cloud using Google’s custom-designed Tensor Processing Unit (TPU).

Per Google’s official website, the cost of using its most advanced TPU can be less than USD 2 per hour if reserved three years in advance. Google first introduced the TPU in 2015 for internal use, and it became available to the public in 2017.

Additionally, per a report from wccftech, Google’s ARM-based TPU v5p “Axion,” designed specifically for data centers, is also rumored to be manufactured using TSMC’s enhanced 3nm process, N3E.

Read more

• [News] Google’s Tensor G5 Reportedly Manufactured with TSMC’s 3nm and InFO-POP Packaging
• [News] Breaking Apple’s Monopoly – TSMC’s InFO Packaging Reportedly Adds Google Chips

(Photo credit: Google)

Google has accelerate its pace on the Pixel series, as the tech giant launched Google Pixel 9 on August 13th, which is two months ahead of its schedule.

Though the Tensor G4 processor in the model is manufactured with Samsung’s 4nm, according to a report citing sources by Commercial Times, Google is said to be switching to TSMC’s 3nm process with its next-generation Tensor G5, coupling with the foundry giant’s InFO-POP packaging.

Google’s Pixel 8 is said to be the first AI-centric smartphone, featuring a range of AI functionalities. Yet, Commercial Times’ report has indicated that, after years of close collaboration, Google will part ways with Samsung and have TSMC produce the Tensor G5 chip.

The chip is also said to adopt TSMC’s advanced InFO-POP packaging. Google’s move, according to the report, demonstrates its ambition to expand its leadership in software to hardware, as it eyes for the opportunities of edge AI.

Industry sources cited by the report further point out that in the fourth quarter, both Qualcomm and MediaTek will launch flagship-level chips, while Apple’s A18 will also be produced using TSMC’s N3 process.

All these developments have hinted at tech giants’ ambition on the massive potential of the edge AI market. Now, Google would be the latest competitor to join the race.

Meanwhile, though Pixel’s market share is relatively low, the Android ecosystem, with its 70% market share in smartphones and billions of users, offers significant potential. Google is said to be following a path similar to Apple’s, achieving complete integration of hardware and software to maximize this potential.

Google’s self-developed chip extends beyond mobile devices, with its TPU (Tensor Processing Unit) now in their seventh generation. Additionally, Google’s Arm-based CPUs are being developed in partnership with TSMC.

Read more

• [News] Breaking Apple’s Monopoly – TSMC’s InFO Packaging Reportedly Adds Google Chips
• [News] TSMC Pushes for FOPLP Mass Production by 2027, Reportedly Eyeing on Innolux’s Plant

(Photo credit: Google)

TSMC’s fan-out (InFO) packaging process will no longer be exclusively used by Apple. According to a report from Commercial Times, it’s revealed that Google’s self-developed Tensor chips for their phones will switch to TSMC’s 3nm process next year and will also start using InFO packaging.

TSMC developed InFO packaging based on FOWLP (fan-out wafer-level packaging), which gained prominence after being adopted by the A10 processor in the iPhone 7 in 2016.

TSMC indicated that the current InFO_PoP technology has advanced to its ninth generation. Last year, it successfully certified 3nm chips, achieving higher efficiency and lower power consumption for mobile devices. The InFO_PoP technology, which features a backside redistribution layer (RDL), has entered mass production this year.

According to industry sources cited by the Commercial Times, Google will shift to TSMC for the Tensor G5 chips, which will be used in the Pixel 10 series next year. These chips will not only utilize the 3nm process but will also adopt integrated fan-out packaging.

This year’s Tensor G4 chips, set to be announced soon, use Samsung’s FOPLP (fan-out panel-level packaging). Although wafer-level packaging (WLP) is generally considered to have advantages over panel-level packaging (PLP), FOWLP still prevails at this stage due to yield and cost considerations.

TSMC has also begun developing FOPLP technology. Previously, per sources cited by a report from MoneyDJ, TSMC has officially formed a team, currently in the “Pathfinding” phase, and is planning to establish a mini line with a clear goal of advancing beyond traditional methods.

Although it is not expected to mature within the next three years, major customers like NVIDIA have partnered with foundry companies to develop new materials. One of TSMC’s major clients has already provided specifications for using glass materials.

Traditionally, chip advancements have been achieved through more advanced process nodes. However, new materials could enable the integration of more transistors on a single chip, achieving the same goal of scaling.

For instance, Intel plans to use glass substrates by 2030, potentially allowing a single chip to house one trillion transistors – 50 times the number in Apple’s A17 Pro processor. This suggests that glass substrates could become a significant milestone in chip development.

Another sources cited by Commercial Times have also indicated that glass substrates are part of the medium- to long-term technological roadmap. They can address challenges in large-size, high-density interconnect substrate development.

Currently, this technology is in the early stages of research and development. Its impact on ABF (Ajinomoto Build-up Film) substrates is expected to become significant in the second half of 2027 or later.

Read more

• [News] TSMC Pushes for FOPLP Mass Production by 2027, Reportedly Eyeing on Innolux’s Plant
• [News] TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road

(Photo credit: TSMC)