Regarding the continuous struggle of its foundry business, Samsung has reportedly decided to make another move, as its semiconductor division (DS) plans to undertake a major organizational restructuring within the year, according to a report by Chosun Biz.

Through the restructuring, DS Division President (Vice Chairman) Jeon Young-hyun is said to focus on addressing major issues related to organizational culture, such as the lack of communication between departments and team self-interest, the report notes.

The revelation follows Samsung’s reported up to 30% layoffs in overseas workforce last week, as noted by Reuters. The plan, set to be implemented by the end of this year, will affect jobs across the Americas, Europe, Asia, and Africa.

Citing industry sources, the report indicates that Samsung Electronics’ DS division plans to strengthen collaboration processes by integrating existing team-based structures into a project-centered model, with an aim to resolve issues arising from the siloed operation of departments.

As a comprehensive semiconductor company with a broad range of businesses, Samsung faces quite a few challenges, while the proliferation of business units and task forces leads to competition and friction between departments. In the development of chips or processes, differing interests among departments—such as semiconductor design, fabrication, and reliability evaluation—can cause communication problems, which may ultimately lead to business failures.

Samsung has been fighting to catch up with its rivals, not only in the foundry sector but in memory as well. Chosun Biz notes that the Korean semiconductor giant is lagging behind competitors in areas like high-bandwidth memory (HBM), cutting-edge DRAM, and foundry technology over the past 2-3 years, which may be attributed to this organizational culture.

Samsung’s foundry division has been working out to mass-produce 3-nm GAA (Gate-All-Around) technology for around three years but still struggles with customer acquisition. A report by The Korea Times states that the yield for Samsung’s 3nm process remained in the single digits until Q1 this year, and slightly improved to about 20% in Q2, though still significantly below the 60% threshold generally needed for mass production.

In terms of DRAM, Samsung seems to gradually lose the leading edge as it has started to fall behind SK hynix, especially in the HBM market. In its latest attempt, Samsung teams up with its foundry rival, TSMC, on the development of HBM4, according to Business Korea.

Moreover, Samsung is facing challenges on the DDR5 DRAM market. Chosun Biz suggests that discrepancies between the quality goals set by the development department and the actual specifications of the mass-produced product delayed Samsung’s entry into the server DDR5 DRAM market by more than 3-6 months, compared to SK hynix.

The report took its setback in the 10-nm 5th generation (1b) DDR5 server DRAM last year as an example. The product, which supplied to Intel, failed to meet the promised performance and was deemed substandard.

In early September, another report by Korean media outlet ZDNet reveals that the tech giant might be facing difficulties in its cutting-edge mobile DRAM, as Samsung’ Mobile eXperience (MX) Division reportedly raised concerns with the DS Division about delays in the delivery of 1b-based LPDDR (low-power DRAM) samples, which are intended to be used in the Galaxy S25 series.

A Samsung Electronics spokesperson cited by Chosun Biz admitted that there continues to be a disconnection between the departments developing new processes and those responsible for mass production, with serious issues arising from the shifting of blame for failures.

However, would Samsung’s latest effort work out? An industry insider cited by the report notes that Intel has attempted to make a change through the “IDM 2.0” strategy over the past three years, but solving these issues in a short period of time has proven difficult. He suggests that it is necessary to go beyond just restructuring to fundamentally change the organization.

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• [News] Samsung Partners with TSMC, Its Foundry Rival, on HBM4 Development
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(Photo credit: Samsung)

Recently, TSMC updated the progress of the expansion of its sub-2nm advanced process. On September 11, Hsu Mao-hsin, Director-General of Taiwan’s Central Taiwan Science Park Administration, announced the expansion of the Taichung Phase 2 park.

Currently, 95% of the land required for TSMC’s plant construction has been secured through agreed purchase prices. The full transaction is expected to be completed by the end of this year, with the land ready for TSMC by the first quarter of next year.

The Phase 2 park covers 89 hectares, of which the Hsingnong Golf Course occupies 67 hectares, representing about 76.8% of the total area and making it the largest landholder. The budget for land acquisition is approximately TWD 23.7 billion.

Currently, there are 111 landowners and structures in the park, with 70% of the owners agreeing to the acquisition, covering 95% of the total area.

In addition to supporting TSMC’s new plant, the rest of around 3 hectares are available for related industries to apply for residency. Several companies in semiconductor supply chain and precision machinery industry have already expressed interest in moving in, and the Central Taiwan Science Park Administration is encouraging IC design companies to join.

Presently, TSMC has concentrated most of its advanced process manufacturing facilities in Taiwan. Aside from three 2nm wafer fabs in its Kaohsiung Nanzi Park, there is also space available to accommodate sub-2nm technology fabs. Industry insiders revealed that Kaohsiung is already preparing for the deployment of the A14 (14 angstrom) process. The first 2nm fab in Nanzi is expected to start mass production in 2025.

Although 2nm product is still absent from the market, their output value is expected to surpass that of 3nm. Insiders indicated that future applications will include HPC (high-performance computing) and smartphone technology sectors.

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(Photo credit: TSMC)

In a last-ditch effort before the upcoming board meeting this week, Intel is said to be seeking assistance from the U.S. government. The latest report by CNBC notes that Intel CEO, Pat Gelsinger, turned to Commerce Secretary Gina Raimondo recently, expressing his disappointment with the heavy dependence of U.S. companies on TSMC, the Taiwanese foundry heavyweight.

According to CNBC, after meeting with Intel, Raimondo followed up by meeting with several public market investors to emphasize the significance of U.S. chip manufacturing amid the rising geopolitical risks surrounding Taiwan. Her aim was to encourage shareholders in companies like NVIDIA and Apple to understand the economic advantages of having a U.S.-based foundry capable of producing AI chips, the sources cited by the report said.

Interesting enough, Jensen Huang, CEO of NVIDIA, mentioned yesterday that the U.S. chip giant heavily relies on TSMC for producing its most important chips, saying TSMC’s agility and ability to respond to demand are incredible. Thus, shifting orders to other suppliers could reportedly lead to a decline in chip quality.

Intel has introduced its Lunar Lake processors in early September, with the target to shake up the AI PC market. However, the chips are outsourced to TSMC, manufactured with the foundry giant’s 3nm node.

Getting stuck in its current situation, Intel is said to be pushing U.S. officials to expedite the release of funding, another report by Bloomberg notes. Earlier in April, Intel and Biden administration announced up to USD 8.5 billion in direct funding under the CHIPS Act.

The company is slated to receive USD 8.5 billion in grants and USD 11 billion in loans under the 2022 Chips and Science Act, but this funding is contingent on meeting key milestones and undergoing extensive due diligence, according to Bloomberg. Therefore, like other potential beneficiaries, Intel has not yet received any money.

An official cited by CNBC said that disbursements are anticipated by the end of the year.

Both the U.S. Commerce Department and an Intel spokesperson declined to comment, according to CNBC.

Regarding the latest development of Intel’s plan to shedding more than 15% of its workforce, a report by CTech notes that Intel may lay off over 1,000 employees in Israel as global cuts begin.

CTech states that Intel has been mindful of geopolitical factors and the timing of local holidays in Israel. Therefore, it would be rather unexpected for the company to initiate layoffs in the country before or during the holiday season, which begins in early October and extends through most of the month.

Citing Gelsinger’s remarks, the report notes that the restructuring process will continue until the end of the year, allowing Intel’s Israeli branch a window of time to start the layoffs after the holidays.

Read more

• [News] CEO Jensen Huang Highlights Strong Demand, Stating that Everyone is Counting on NVIDIA
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(Photo credit: Intel)

ACM Research, Inc., a provider of wafer processing solutions for semiconductor and advanced wafer-level packaging applications in China, announced on September 3rd the release of its Ultra C bev-p panel bevel etching tool for fan-out panel-level packaging (FOPLP) applications.

This new tool is designed for bevel etching and cleaning in copper-related processes, offering dual-side bevel etching for both the front and back of panels within a single system, further boosting process efficiency and enhances product reliability.

Moreover, a day after the announcement, the company further revealed that it had received purchase orders for four wafer-level packaging tools, including two from a U.S.-based customer and two from a U.S.-based research and development (R&D) center.

Dr. David Wang, ACM’s president and chief executive officer, believes that FOPLP will grow in importance as it addresses the evolving needs of modern electronic applications, offering benefits in integration density, cost efficiency, and design flexibility.

Reportedly, the new Ultra C bev-p tool is designed to deliver advanced performance, utilizing ACM’s expertise in wet processing. It is one of the first tools to incorporate double-sided bevel etching for horizontal panel applications.

Together with the Ultra ECP ap-p for electrochemical plating and the Ultra C vac-p flux cleaning tools, the Ultra C bev-p is expected to support the FOPLP market by enabling advanced packaging on large panels with high-precision features.

ACM emphasizes that the Ultra C bev-p tool is a critical enabler for FOPLP processes, employing a wet etching technique tailored for bevel etching and copper residue removal.

This process plays a vital role in preventing electrical shorts, reducing contamination risks, and preserving the integrity of subsequent processing steps, ensuring long-term device reliability. The tool’s effectiveness is driven by ACM’s patented technology, designed to tackle the specific challenges of square panel substrates.

Different from traditional round wafers, ACM’s design is said to ensure precise bevel removal process that stays confined to the bevel region, even on warped panels. This is essential for maintaining the integrity of the etching process while ensuring the high performance and reliability needed for advanced semiconductor technologies.

Currently, major players in the FOPLP advanced packaging field include Powertech Technology, ASE Group, SPIL, TSMC, Innolux, JSnepes, and Samsung Electro-Mechanics.

TrendForce points out that FOPLP technology presents advantages and disadvantages. Its main strengths are lower unit cost and larger package size, but as its technology and equipment systems are still developing, the commercialization process is highly uncertain.

It is estimated that the mass production timeline for FOPLP in consumer IC and AI GPU may fall between the second half of 2024 to 2026, and 2027-2028, respectively.

Read more

• [News] ACM Research Steps into FOPLP Advanced Packaging Field
• [News] TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road 

(Photo credit: ACMR)

While Samsung Electronics is said to be delivering an oversea workforce cut up to 30%, a report from Korean media outlet Business Korea on September 11th has added that persistent issues with its 2nm yield rate have led Samsung to decide to withdraw personnel from its Taylor, Texas plant, signaling another setback for its advanced wafer foundry business.

Originally envisioned as a mass production hub for advanced processes below 4nm, the Taylor facility’s strategic location near major tech companies was intended to attract U.S. clients. However, despite rapid development, Samsung continues to face 2nm yield issues, resulting in performance and production capacity falling short of its main competitor, TSMC.

Reportedly, Samsung’s wafer foundry yield is below 50%, particularly in processes below 3nm, while TSMC’s advanced process yield is around 60-70%. This gap has widened the market share difference between the two companies.

As per a report from TrendForce, TSMC held a 62.3% share of the global wafer foundry market in the second quarter, while Samsung’s market share was only 11.5%.

Industry sources cited by Business Korea further added that Samsung’s Gate-All-Around (GAA) yield is around 10-20%, which is insufficient for handling orders and mass production. Such yields have forced Samsung to reconsider its strategy and withdraw personnel from the Taylor plant, leaving only a minimal number of staff.

Samsung Electronics had signed a preliminary agreement to receive up to KRW 9 trillion in subsidies from the U.S. Chips Act. However, a key condition for receiving the funding is that the plant must operate smoothly, and Samsung’s current difficulties put this agreement at risk.

Reportedly, Samsung Chairman Lee Jae-Yong personally visited major equipment suppliers like ASML and Zeiss, hoping to achieve breakthroughs in process and yield improvements. However, there have been no significant results so far, and it remains uncertain when personnel might be reassigned back to the Taylor plant.

Read more

• [News] Samsung Reportedly Buckling Under Pressure, with Plans to Cut Overseas Workforce by Up to 30%
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(Photo credit: Samsung)