In a last-ditch effort before the upcoming board meeting this week, Intel is said to be seeking assistance from the U.S. government. The latest report by CNBC notes that Intel CEO, Pat Gelsinger, turned to Commerce Secretary Gina Raimondo recently, expressing his disappointment with the heavy dependence of U.S. companies on TSMC, the Taiwanese foundry heavyweight.

According to CNBC, after meeting with Intel, Raimondo followed up by meeting with several public market investors to emphasize the significance of U.S. chip manufacturing amid the rising geopolitical risks surrounding Taiwan. Her aim was to encourage shareholders in companies like NVIDIA and Apple to understand the economic advantages of having a U.S.-based foundry capable of producing AI chips, the sources cited by the report said.

Interesting enough, Jensen Huang, CEO of NVIDIA, mentioned yesterday that the U.S. chip giant heavily relies on TSMC for producing its most important chips, saying TSMC’s agility and ability to respond to demand are incredible. Thus, shifting orders to other suppliers could reportedly lead to a decline in chip quality.

Intel has introduced its Lunar Lake processors in early September, with the target to shake up the AI PC market. However, the chips are outsourced to TSMC, manufactured with the foundry giant’s 3nm node.

Getting stuck in its current situation, Intel is said to be pushing U.S. officials to expedite the release of funding, another report by Bloomberg notes. Earlier in April, Intel and Biden administration announced up to USD 8.5 billion in direct funding under the CHIPS Act.

The company is slated to receive USD 8.5 billion in grants and USD 11 billion in loans under the 2022 Chips and Science Act, but this funding is contingent on meeting key milestones and undergoing extensive due diligence, according to Bloomberg. Therefore, like other potential beneficiaries, Intel has not yet received any money.

An official cited by CNBC said that disbursements are anticipated by the end of the year.

Both the U.S. Commerce Department and an Intel spokesperson declined to comment, according to CNBC.

Regarding the latest development of Intel’s plan to shedding more than 15% of its workforce, a report by CTech notes that Intel may lay off over 1,000 employees in Israel as global cuts begin.

CTech states that Intel has been mindful of geopolitical factors and the timing of local holidays in Israel. Therefore, it would be rather unexpected for the company to initiate layoffs in the country before or during the holiday season, which begins in early October and extends through most of the month.

Citing Gelsinger’s remarks, the report notes that the restructuring process will continue until the end of the year, allowing Intel’s Israeli branch a window of time to start the layoffs after the holidays.

Read more

• [News] CEO Jensen Huang Highlights Strong Demand, Stating that Everyone is Counting on NVIDIA
• [News] Intel Reportedly Outsources All Sub-3nm Process Production to TSMC

(Photo credit: Intel)

ACM Research, Inc., a provider of wafer processing solutions for semiconductor and advanced wafer-level packaging applications in China, announced on September 3rd the release of its Ultra C bev-p panel bevel etching tool for fan-out panel-level packaging (FOPLP) applications.

This new tool is designed for bevel etching and cleaning in copper-related processes, offering dual-side bevel etching for both the front and back of panels within a single system, further boosting process efficiency and enhances product reliability.

Moreover, a day after the announcement, the company further revealed that it had received purchase orders for four wafer-level packaging tools, including two from a U.S.-based customer and two from a U.S.-based research and development (R&D) center.

Dr. David Wang, ACM’s president and chief executive officer, believes that FOPLP will grow in importance as it addresses the evolving needs of modern electronic applications, offering benefits in integration density, cost efficiency, and design flexibility.

Reportedly, the new Ultra C bev-p tool is designed to deliver advanced performance, utilizing ACM’s expertise in wet processing. It is one of the first tools to incorporate double-sided bevel etching for horizontal panel applications.

Together with the Ultra ECP ap-p for electrochemical plating and the Ultra C vac-p flux cleaning tools, the Ultra C bev-p is expected to support the FOPLP market by enabling advanced packaging on large panels with high-precision features.

ACM emphasizes that the Ultra C bev-p tool is a critical enabler for FOPLP processes, employing a wet etching technique tailored for bevel etching and copper residue removal.

This process plays a vital role in preventing electrical shorts, reducing contamination risks, and preserving the integrity of subsequent processing steps, ensuring long-term device reliability. The tool’s effectiveness is driven by ACM’s patented technology, designed to tackle the specific challenges of square panel substrates.

Different from traditional round wafers, ACM’s design is said to ensure precise bevel removal process that stays confined to the bevel region, even on warped panels. This is essential for maintaining the integrity of the etching process while ensuring the high performance and reliability needed for advanced semiconductor technologies.

Currently, major players in the FOPLP advanced packaging field include Powertech Technology, ASE Group, SPIL, TSMC, Innolux, JSnepes, and Samsung Electro-Mechanics.

TrendForce points out that FOPLP technology presents advantages and disadvantages. Its main strengths are lower unit cost and larger package size, but as its technology and equipment systems are still developing, the commercialization process is highly uncertain.

It is estimated that the mass production timeline for FOPLP in consumer IC and AI GPU may fall between the second half of 2024 to 2026, and 2027-2028, respectively.

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• [News] ACM Research Steps into FOPLP Advanced Packaging Field
• [News] TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road 

(Photo credit: ACMR)

While Samsung Electronics is said to be delivering an oversea workforce cut up to 30%, a report from Korean media outlet Business Korea on September 11th has added that persistent issues with its 2nm yield rate have led Samsung to decide to withdraw personnel from its Taylor, Texas plant, signaling another setback for its advanced wafer foundry business.

Originally envisioned as a mass production hub for advanced processes below 4nm, the Taylor facility’s strategic location near major tech companies was intended to attract U.S. clients. However, despite rapid development, Samsung continues to face 2nm yield issues, resulting in performance and production capacity falling short of its main competitor, TSMC.

Reportedly, Samsung’s wafer foundry yield is below 50%, particularly in processes below 3nm, while TSMC’s advanced process yield is around 60-70%. This gap has widened the market share difference between the two companies.

As per a report from TrendForce, TSMC held a 62.3% share of the global wafer foundry market in the second quarter, while Samsung’s market share was only 11.5%.

Industry sources cited by Business Korea further added that Samsung’s Gate-All-Around (GAA) yield is around 10-20%, which is insufficient for handling orders and mass production. Such yields have forced Samsung to reconsider its strategy and withdraw personnel from the Taylor plant, leaving only a minimal number of staff.

Samsung Electronics had signed a preliminary agreement to receive up to KRW 9 trillion in subsidies from the U.S. Chips Act. However, a key condition for receiving the funding is that the plant must operate smoothly, and Samsung’s current difficulties put this agreement at risk.

Reportedly, Samsung Chairman Lee Jae-Yong personally visited major equipment suppliers like ASML and Zeiss, hoping to achieve breakthroughs in process and yield improvements. However, there have been no significant results so far, and it remains uncertain when personnel might be reassigned back to the Taylor plant.

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• [News] Samsung Reportedly Buckling Under Pressure, with Plans to Cut Overseas Workforce by Up to 30%
• [News] Samsung Signals Will to Collaborate with Other Foundries on Basedie

(Photo credit: Samsung)

On September 9, Indian tech blog PiunikaWeb cited a report from Tech & Leaks Zone, stating that rumors have hinting at Google’s preparation to exit Samsung Electronics’ wafer foundry business, Samsung Foundry, and switch to TSMC in 2025. The next two generations of Google’s custom Tensor processors are reportedly expected to use TSMC’s 3nm and 2nm processes, respectively.

As per the same report, Google’s Tensor G4 processor is being manufactured by Samsung Foundry using its 4nm process. However, the G4 offers only a slight upgrade compared to the Tensor G3 in the Pixel 8 smartphone, as the G4 continues to use Samsung’s older FO-PLP packaging technology instead of the newer FO-WLP packaging, which is more capable in preventing overheating.

On the other hand, Google’s Tensor G5, which will be used in the Pixel 10, is reportedly set to be manufactured by TSMC using the latest 3nm process and TSMC’s advanced InFO-POP packaging technology. The Tensor G6, which will support the Pixel 11 series, will also be produced by TSMC using 2nm process.

Notably, Apple had introduced an AI technical document in June, disclosed that two AI models supporting “Apple Intelligence” were trained in the cloud using Google’s custom-designed Tensor Processing Unit (TPU).

Per Google’s official website, the cost of using its most advanced TPU can be less than USD 2 per hour if reserved three years in advance. Google first introduced the TPU in 2015 for internal use, and it became available to the public in 2017.

Additionally, per a report from wccftech, Google’s ARM-based TPU v5p “Axion,” designed specifically for data centers, is also rumored to be manufactured using TSMC’s enhanced 3nm process, N3E.

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• [News] Google’s Tensor G5 Reportedly Manufactured with TSMC’s 3nm and InFO-POP Packaging
• [News] Breaking Apple’s Monopoly – TSMC’s InFO Packaging Reportedly Adds Google Chips

(Photo credit: Google)

As silicon photonics has become a key technology in the AI era, semiconductor giants, including Intel and TSMC, have joined the battlefield. Now another tech giant has engaged in the war, while U.S. chip giant AMD is reportedly seeking silicon photonics partners in Taiwan, according to local media United Daily News.

According to the report, AMD has reached out to Taiwanese rising stars in the sector, including BE Epitaxy Semiconductor and best Epitaxy Manufacturing Company. The former focuses on the design, research and development of silicon photonics platforms, while the latter possesses MOCVD machines to produce 4-inch and 6-inch epitaxy wafers.

Regarding the rumor, AMD declined to comment. Recently, the AI chip giant announced a USD 4.9 billion acquisition of server manufacturer ZT Systems to strengthen its AI data center infrastructure, with the aim to further enhance its system-level R&D capability. Now it seems that AMD is also eyeing to set foot in the market, as silicon photonics is poised to be a critical technology in the future.

Earlier in July, AMD is said to establish a research and development (R&D) center in Taiwan, which will focus on several advanced technologies, including silicon photonics, artificial intelligence (AI), and heterogeneous integration.

Here’s why the technology matters: As chipmakers keep pushing the boundaries of Moore’s Law, leading to increased transistor density per unit area, signal loss issues inevitably arise during transmission since chips rely on electricity to transmit signals. Silicon photonics technology, on the other hand, by replacing electrical signals with optical signals for high-speed data transmission, successfully overcomes this challenge, achieving higher bandwidth and faster data processing.

On September 3, a consortium of more than 30 companies, including TSMC, announced the establishment of the Silicon Photonics Industry Alliance (SiPhIA) at SEMICON.

According to a previous report by Nikkei, TSMC and its supply chain are accelerating the development of next-generation silicon photonic solutions, with plans to have the technology ready for production within the next three to five years.

AMD’s major rival, NVIDIA, is reportedly collaborating with TSMC to develop optical channel and IC interconnect technologies.

On the other hand, Intel has been developing silicon photonics technology for over 30 years. Since the launch of its silicon photonics platform in 2016, Intel has shipped over 8 million photonic integrated circuits (PICs) and more than 3.2 million integrated on-chip lasers, according to its press release. These products have been adopted by numerous large-scale cloud service providers.

Interestingly enough, Intel has also been actively collaborating with Taiwanese companies in the development of silicon photonics, United Daily News notes. One of its most notable partners is LandMark Optoelectronics, which supplies Intel with critical upstream silicon photonics materials, such as epitaxial layers and related components.

Read more

• [News] Silicon Photonics Reshapes the Future; TSMC, ASE Ready to Seize Market Share
• [News] TSMC’s Latest Advancements in CFET, 3D Stacking, and Silicon Photonics

(Photo credit: AMD)