Amid the AI boom driving a surge in demand for advanced packaging, Samsung Electronics announced in March its ambition to achieve record-high revenue for the business this year, aiming to surpass the USD 100 million mark. The company, which is eager to catch up with TSMC not only on the foundry but also the advanced packaging business, was said to hire former TSMC deputy director Vic Lin as Vice President of the Advanced Packaging Business Unit in its semiconductor department. However, according to a report by ijiwei, the business unit has been disbanded recently, and rumor has it that Chinese semiconductor companies are attempting to recruit Lin.

It is worth noting that before joining TSMC, Lin worked at Micron Technology. Afterwards, during his 19-year tenure at TSMC from 1999 to 2017, Lin was responsible for the application of the semiconductor giant’s over 450 U.S. patents, the report notes. His major accomplishments included securing a major collaboration deal with Apple, as well as laying a solid foundation for TSMC’s expertise in 3D packaging technology.

Nowadays, the advanced packaging business has emerged as one of TSMC’s major growth momentum, with primary customer NVIDIA having the highest demand, occupying about half of the capacity, followed closely by AMD. As the demands for AI and HPC processors keep booming, TSMC revealed plans earlier to further expand its chip-on-wafer-on-substrate (CoWoS) capacity at a compound annual rate (CAGR) of over 60% until at least 2026, according to a report by AnandTech.

After leaving TSMC, Lin became the CEO of Skytech, where his extensive work experience helped him accumulate substantial expertise in packaging equipment manufacturing.

In 2022, Samsung established an Advanced Packaging Task Force, which was later transformed to its Advanced Packaging Business Team in 2023, of which Lin was said to join the team as Vice President, ijiwei notes.

However, industry insiders have revealed that the team was recently disbanded, and its members have returned to Samsung’s memory department and others, the report suggests. Additionally, Lin’s two-year contract with Samsung is said to be expire soon, and it seems unlikely that Samsung will renew it.

Being regarded as a “semiconductor packaging expert,” Lin’s next move is being closely watched. Certain Chinese semiconductor companies are rumored to get in contact with Lin, but it is expected that he will prioritize opportunities to collaborate with semiconductor companies in Taiwan, the report indicates.

The report notes that Samsung has confirmed that the team had been disbanded due to an internal organizational restructuring but declined to comment on personnel matters.

Earlier in May, as part of the restructuring process, the company has disbanded its Robot Business Team as well, which was responsible for developing its first wearable robot, “Bot Fit.”

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• [News] Samsung to Intensify Efforts for Capturing Intel’s Advanced Packaging Orders Shifting from TSMC
• [News] Samsung Reportedly Commits to Advanced Packaging, Targets Over USD100 Million in Related Revenue This Year

(Photo credit: Samsung)

TSMC is accelerating its global expansion, receiving robust support from governments in Japan and China. In the first half of this year alone, TSMC secured nearly NT$8 billion in subsidies from the two countries, bringing its total government aid from Japan and China to NT$62.5 billion(approximately USD $1.96 billion).

According to the Central News Agency, TSMC’s financial reports show that its subsidiaries—JASM in Japan and Nanjing in China—received these subsidies to support their plans to establish and operate manufacturing facilities in Kumamoto and Nanjing. The funds are primarily earmarked for real estate, plant, and equipment purchases, as well as to offset construction and operational costs.

TSMC reported that it received NT$7.051 billion in subsidies from Japan and China in 2022, followed by NT$47.545 billion in 2023, and an additional NT$7.956 billion in the first half of this year, totaling NT$62.5 billion.

Governments worldwide have increasingly recognized semiconductors as vital strategic assets, spurring a race to subsidize the industry’s growth. With TSMC’s cutting-edge technology leading the global market, it has become a key target for investment incentives from various governments. TSMC has already established a presence in Kumamoto, Japan, and Arizona, U.S., and is expanding its 28nm capacity in China.

On August 20, TSMC broke ground on its European Semiconductor Manufacturing Company (ESMC) in Dresden, Germany, marking the start of its initial land preparation phase for a new wafer fab. This expansion extends TSMC’s global footprint from the U.S., China, and Japan to Europe.

The groundbreaking ceremony, hosted by TSMC Chairman C.C. Wei, was attended by German Chancellor Olaf Scholz and European Commission President Ursula von der Leyen. The European Commission also announced its approval of a €5 billion German subsidy package under EU state aid rules, demonstrating its support for the ESMC project.

TSMC’s Kumamoto plant is progressing rapidly, with its first wafer fab set to begin mass production of 12nm, 16nm, 22nm, and 28nm process technologies in the fourth quarter of this year. A second fab is scheduled to start production in 2027, utilizing 6nm, 7nm, 12nm, 16nm, and 40nm process technologies.

In Arizona, TSMC’s first wafer fab is on track to begin 4nm process production in the first half of 2025, with a second fab expected to commence 2nm production in 2028. The company also plans to construct a third fab that will deploy 2nm or more advanced technologies.

In April, the U.S. Department of Commerce announced a USD $6.6 billion subsidy for TSMC’s advanced fab in Arizona. However, TSMC has yet to receive these funds and does not speculate on future government subsidies.

(Photo credit: TSMC)

According to a report from the Commercial Times, SK hynix is expected to announce a plan of closer collaboration with TSMC and NVIDIA during the Semicon Taiwan exhibition in September, which is likely to focusing on the development of next-generation HBM. This partnership is expected to further strengthen their leadership in the supply of critical components for AI servers.

Semicon Taiwan will be held from September 4 to 6, and sources cited by the same report indicate that SK hynix President Justin Kim will attend the event and deliver a keynote speech for the first time.

Upon arriving in Taiwan, Justin Kim is expected to meet with TSMC executives. The report, citing rumors, suggests that NVIDIA CEO Jensen Huang might also join the meeting, further strengthening the alliance among the tech giants.

The core of this collaboration will revolve around HBM technology. In the past, SK hynix used its own processes to manufacture base dies up to HBM3e (the fifth-generation HBM).

However, industry sources cited by the report reveal that SK hynix will adopt TSMC’s logic process to manufacture the base die starting from HBM4, which would allow the memory giant to customize products for its clients in terms of performance and efficiency.

Industry sources cited by the report also indicate that SK hynix and TSMC have agreed to collaborate on the development and production of HBM4, scheduled for mass production in 2026.

This collaboration will reportedly involve manufacturing HBM4 interface chips using 12FFC+ (12nm class) and 5nm processes to achieve smaller interconnect spacing and enhance memory performance for AI and high-performance computing (HPC) processors.

Per SK hynix’s product roadmap, the company plans to launch a 12-layer stacked HBM4 in the second half of 2025 and 16-layer in 2026. TSMC, on the other hand, is also working to strengthen and expand its CoWoS-L and CoWoS-R packaging capacity to support the large-scale production of HBM4.

SK hynix has been the major supplier of HBM for NVIDIA’s AI GPUs, and with the upcoming Rubin series planned for 2026, it is expected to adopt HBM4 12Hi with 8 clusters per GPU. This partnership between SK hynix, TSMC and NVIDIA, therefore, is expected to expanding its influence and widening the gap with Samsung.

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• [News] SK hynix, TSMC, and NVIDIA Reportedly Forge Alliance to Develop Next-Generation HBM
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(Photo credit: SK hynix)

Earlier in June, Samsung updated its roadmap in the Angstrom era, stating that its 2nm node optimized with backside power delivery network (BSPDN), referred to as SF2Z, will enter mass production in 2027. Now, according to the latest report by the Korea Economic Daily, compared with the traditional front-end power delivery technology, BSPDN is said to reduce the size of Samsung’s 2nm chip by 17%.

Citing Lee Sungjae, vice president of the Foundry PDK Development Team at Samsung, on Thursday, the report also notes that by applying BSPDN to its 2nm chips, Samsung is expected to improve the product’s performance and power efficiency by 8% and 15%, respectively.

Lee’s remarks was the first time a Samsung foundry business executive provided details publicly regarding its BSPDN roadmap. The report explains that by positioning the power rails on the back of the wafer to remove bottlenecks between power and signal lines, the production of smaller chips would be easier.

However, Samsung is not the first semiconductor giant to adopt this technology. Among the Big Three in the foundry sector, Intel is at the forefront, aiming to produce chips with BSPDN technology, which it calls PowerVia, with Intel 20A (2 nm) in 2024. The tech giant also plans to implement PowerVia on Intel’s 20A along with the RibbonFET architecture for the full-surround gate transistor.

According to Intel, power lines typically occupy around 20% of the space on the chip surface, while its self-developed PowerVia’s backside power delivery technology saves this space, allowing more flexibility in the interconnect layers.

On the other hand, foundry leader TSMC reportedly plans to integrate its backside power delivery technology, Super PowerRail architecture, and nanosheet transistors in its A16 chip in 2026.

In addition to BSPDN, Samsung also revealed its roadmap about the next-generation gate-all-around (GAA) technology, which the company was first introduced in 2022, according to the report.

Samsung plans to begin mass production of 3 nm chips based on its second-generation GAA technology (SF3) in 2H24 and will also implement GAA in its upcoming 2 nm process, the report notes.

According to Lee, SF3 has enhanced chip performance by 30%, improved power efficiency by 50%, and reduced chip size by 35% compared to the chips produced with the first-generation GAA process. Coupling with the adoption of BSPDN, the two technologies can further reduce the chip size for Samsung.

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• [News] Samsung Unveils Next-gen 2nm Node Roadmap; SF2Z with Backside Power Delivery to Enter Production in 2027
• [News] TSMC’s Backside Power Delivery Reportedly Set for 2026, Benefiting the Supply Chain

(Photo credit: Samsung)

HBM4, the sixth generation of HBM, is poised to become the key to breakthroughs in computing power for next-generation CSPs (Cloud Service Providers). According to a report from Commercial Times citing Global Unichip Corp. (GUC), to support the development of HBM4, their semiconductor IP (Intellectual Property) is already prepared and awaiting CSP manufacturers to advance their manufacturing processes.

GUC pointed out that if future clients need to integrate general-purpose HBM4 into ASICs (Application-Specific Integrated Circuits), GUC can provide assistance.

GUC further emphasized that its IP is ready for HBM4 development, waiting for CSPs to advance their manufacturing processes. Currently, the ASICs being mass-produced by CSPs still use HBM2 or HBM2e, while HBM3 is in the R&D stage.

The company candidly acknowledged that it cannot play any role at the moment and needs to wait for CSPs to adopt HBM4 on a large scale, taking cost considerations into account. When that time comes, GUC expects to assist CSPs in designing their solutions.

Currently, SK hynix has the technological capability for the general-purpose base die used in HBM4. However, when moving to more advanced processes like 5nm or beyond, external design service providers will be required.

Industry sources cited by Commercial Times believe that the pace of advancements in computing power is accelerating.

For instance, Google’s sixth-generation TPU, expected to be launched by the end of this year, is already based on TSMC’s 4nm process and designed on the Arm architecture.

Similarly, Meta’s upcoming MTIAv2 is built on TSMC’s 5nm process. The trend toward developing in-house chips is characterized by lower power consumption and larger memory capacities.

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• [News] TSMC Reportedly Secures Another AI Opportunity, Winning Order from SK Hynix
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(Photo credit: GUC)