As per a report from Economic Daily News, TSMC’s first European 12-inch fab is set to hold its groundbreaking ceremony on August 20. Along with TSMC’s ongoing projects in Japan and the U.S., the investment has amounted to nearly USD 100 billion. Meanwhile, this move is also expected to generate opportunities for supporting Taiwanese contractors.

The new TSMC facility in Dresden, Germany, is anticipated to use 28/22nm planar CMOS and 16/12nm FinFET process, with a monthly production capacity of approximately 40k 12-inch wafers.

Per TSMC’s plan, its fab in Germany will start operation by the end of 2027, with estimated costs exceeding EUR 10 billion (approximately USD 10.8 billion), creating opportunities in plant equipment and engineering sectors.

In response to the demand, Marketech International, a Taiwanese fab tool maker, has already set up offices and accommodations in Dresden in 2023 and has deployed staff there.

Additionally, Topco Scientific, a Taiwanese semiconductor materials distributor, is also said to be planning to establish a presence in Europe, with plans to set up operations in Prague, Czech Republic, about two hours’ drive from Dresden.

On the other hand, TSMC is accelerating the construction of its Kumamoto plant in Japan, with production scheduled to begin by the end of this year. This facility will be the fastest among TSMC’s new overseas fabs to start production. TSMC is also actively advancing the construction of a second Kumamoto plant.

TSMC plans to invest over USD 20 billion in its two Japanese facilities, which are expected to have a combined monthly capacity of over 100k 12-inch wafers. The plants will offer 40nm, 22/28nm, 12/16nm, and 6/7nm process.

Once operational, the Kumamoto plant is anticipated to generate significant opportunities in the semiconductor inspection sector.

MA-tek, a giant in semiconductor inspection and analysis services, is planning to expand its service at its laboratories in Nagoya and Kumamoto, while setting up a third laboratory to fully meet the needs of local semiconductor clients.

As for TSMC’s fab in Arizona, U.S., the company has planned a total capital expenditure exceeding USD 65 billion. Industry sources cited by Economic Daily News have expected that companies like United Integrated Services and Marketech International will continue to benefit from this investment.

Read more

• [News] TSMC Reports No Major Damage to Kumamoto Plant after 7.1 Magnitude Earthquake near Kyushu, Japan
• [News] TSMC’s German Plant Reported to Break Ground in Weeks, Expected to Begin Production by Late 2027

(Photo credit: TSMC)

On August 13, Google officially released the Pixel 9 series of smartphones, featuring Google’s latest self-developed Tensor G4 processor and advanced AI function supported by Gemini AI.

Google Pixel 9 series includes three full-screen smartphones: Pixel 9, Pixel 9 Pro, and Pixel 9 Pro XL, as well as a foldable smartphone, the Pixel 9 Pro Fold.

Both Pixel 9 and Pixel 9 Pro are equipped with 6.3-inch screens, with the Pixel 9 Pro using a better LTPO screen; Pixel 9 Pro XL is fitted with a 6.8-inch screen; Pixel 9 Pro Fold’s internal screen size increased from 7.6 inches to 8 inches, and the external display screen size from 5.8 inches to 6.3 inches.

The base memory capacity of the new phones is up to 12GB, with the two Pro models and the Pixel 9 Pro Fold offering 16GB of memory.

It is learned that the Tensor G4 adopted in Google’s new phones is based on Samsung’s 4nm process (4LPP+), boasting a 3.1GHz Arm Cortex-X4 super core, three 2.6GHz Arm Cortex-A720 large cores, and four 1.92GHz Arm Cortex-A520 small cores.

Moreover, Tensor G4 is equipped with the new Samsung Exynos Modem 5400 baseband chip (Outside the processor), supporting 4G/5G, WiFi-7, Bluetooth 5.x, and satellite connectivity. The memory used is LPDDR5X, and media decoding supports formats such as H.264, H.265, VP9, and AV1.

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• [News] Google’s Tensor G5 Reportedly Manufactured with TSMC’s 3nm and InFO-POP Packaging
• [News] Google Reportedly Shifts Orders from Samsung to TSMC for Its Upcoming Tensor G5 in the Pixel 10 Series

(Photo credit: Google)

As semiconductor giants, starting with Intel and TSMC, have been bringing in ASML’s High-NA EUV (high-numerical aperture extreme ultraviolet) equipment to accelerate the development in advanced nodes, the elite group has now reportedly been added two new members: Samsung and SK hynix.

According to the reports by Korean media outlet Sedaily and ZDNet, Samsung Electronics’ semiconductor (DS) division is said to bring in High-NA EUV equipment as early as the end of 2024. SK hynix’s High-NA equipment, which is expected to be applied to the mass production of advanced DRAM, will reportedly be introduced in 2026.

Samsung to Introduce First High-NA EUV Machine as soon as Year-End, Eyeing Full Commercialization by 2027

Sedaily, citing industry sources on August 13^th, notes that Samsung is expected to begin bringing in its first High-NA EUV equipment, ASML’s EXE:5000, between the end of this year and the first quarter of next year. It is worth noting that Samsung’s first High-NA EUV equipment is likely to be used for foundry operations, the report reveals.

Among the semiconductor heavyweights which have been advancing in the foundry business, Intel is the first to order new High-NA EUV machines from ASML. In May, Intel was said to have secured its first batch of the new High-NA EUV lithography equipment from ASML, which the company will allegedly use on its 18A (1.8nm) and 14A (1.4nm) nodes.

TSMC, on the other hand, is more concerned on the new machine’s expensiveness, as it might be priced at as much as EUR 350 million (roughly USD 380 million) per unit, according to a previous report by Bloomberg. However, the report, citing ASML’s spokesperson, confirmed that the Dutch chip equipment giant will ship High-NA EUV equipment to TSMC by the end of this year.

Now, following its two major rivals in the foundry sector, Samsung, by introducing High-NA EUV equipment as soon as year-end, aims to boost its competitive edge in the advanced nodes.

As the installation process is quite time-consuming, Samsung aims for the full commercialization of High-NA by 2027, supported by its efforts to build the related ecosystem, the report says.

According to the report, Samsung is working with electronic design automation (EDA) companies to design new types of masks, including curved (curvilinear) circuits for High-NA EUV that improve the sharpness of the printed circuits on wafers. This collaboration includes companies like Synopsys, a global leader in semiconductor EDA tools.

SK hynix’s High-NA EUV Reportedly to be Applied to 0a DRAM Production

According to the report by Sedaily, ASML has produced eight EXE:5000 High-NA EUV units currently, as Intel has the lion’s share by securing multiple units. Samsung is said to be the last customer to place the order for ASML’s first batch of units.

On the other hand, SK hynix, Samsung’s major rival in the memory sector, is reported to bring in ASML’s next generation of High-NA EUV machine, the EXE:5200, in 2026, ZDNet suggests.

Citing industry sources on August 16th, ZDNet notes that the HBM giant has been expanding the personnel dedicated to High-NA EUV development within the company.

Although specific plans, such as the fab where the equipment will be installed or the direction of additional investment, have not been disclosed, it is expected that the technology could be applied to mass production in 0a (single-digit nanometer) DRAM as early as possible, the report indicates.

Read more

• News] TSMC Reportedly Invests over USD 12.3 Billion in EUV, Advancing in 2nm Production
• [News] Intel Secures First Batch of High-NA EUV Equipment from ASML, Ahead of Samsung and SK Hynix

(Photo credit: ASML)

NEO Semiconductor, a company focused on 3D DRAM and 3D NAND memory, has unveiled its latest 3D X-AI chip technology, which could potentially replace the existing HBM used in AI GPU accelerators.

Reportedly, this 3D DRAM comes with built-in AI processing capabilities, enabling processing and generation without the need for mathematical output. When large amounts of data are transferred between memory and processors, it can reduce data bus issues, thereby enhancing AI performance and reducing power consumption.

The 3D X-AI chip has a underlying neuron circuit layer that can process data stored in 300 memory layers on the same chip. NEO Semiconductor states that with 8,000 neutron circuits performing AI processing in memory, the 3D memory performance can be increased by 100 times, with memory density 8 times higher than current HBM. By reducing the amount of data processed in the GPU, power consumption can be reduced by 99%.

A single 3D X-AI die contains 300 layers of 3D DRAM cells and one layer of neural circuits with 8,000 neurons. It also has a capacity of 128GB, with each chip supporting up to 10 TB/s of AI processing capability. Using 12 3D X-AI dies stacked with HBM packaging can achieve 120 TB/s processing throughput. Thus, NEO estimates that this configuration may eventually result in a 100-fold performance increase.

Source: NEO Semiconductor

Andy Hsu, Founder & CEO of NEO Semiconductor, noted that current AI chips waste significant amounts of performance and power due to architectural and technological inefficiencies. The existing AI chip architecture stores data in HBM and relies on a GPU for all calculations.

He further claimed that the separation of data storage and processing architecture has made the data bus an unavoidable performance bottleneck, leading to limited performance and high power consumption during large data transfers.

The 3D X-AI, as per Hsu, can perform AI processing within each HBM chip, which may drastically reduce the data transferred between HBM and the GPU, thus significantly improving performance and reducing power consumption.

Many companies are researching technologies to increase processing speed and communication throughput. As semiconductor speeds and efficiencies continue to rise, the data bus transferring information between components will become a bottleneck. Therefore, such technologies will enable all components to accelerate together.

Source: NEO Semiconductor

As per a report from tom’s hardware, companies like TSMC, Intel, and Innolux are already exploring optical technologies, looking for faster communications within the motherboard. By shifting some AI processing from the GPU to the HBM, NEO Semiconductor may reduce the workload and potentially achieve better efficiency than current power-hungry AI accelerators.

Read more

• [Insights] Memory Spot Price Update: DRAM Spot Trading Remains Limited as DDR4 Spot Prices Continue to Fall
• [News] Samsung and SK hynix to Implement Hybrid Bonding with 3D DRAM

(Photo credit: NEO Semiconductor)

TSMC is significantly expanding its production, continuously increasing its facilities. On August 15, as per a report from Liberty Times Net, the company announced that it had signed a contract with panel manufacturer Innolux to purchase its plant and associated facilities located in the Southern Taiwan Science Park.

The building’s total area exceeds 96,000 square meters, with a transaction value of NTD 17.14 billion, which is much lower than the rumored market price of over NTD 20 billion. TSMC announced that the facility will be used for operations and production.

Innolux recently announced the sale of 4th Plant in Tainan (5.5-generation LCD panel plant). A previous report from Economic Daily News once cited rumors, claiming that both Micron and TSMC have been actively exploring the acquisition.

Moreover, it was also reported that TSMC offered a price 20% higher than the base price, with plans to use the facility to expand its advanced process or advanced packaging capacity.

According to Liberty Times Net citing sources at the Southern Taiwan Science Park, TSMC’s original plant is located in the northwest part of the park, while the newly acquired Innolux plant is situated in the southwest, so they are not adjacent.

TSMC had previously purchased a plant from Hannstar and demolished and rebuilt it, as the planning of panel plants differs from that of fabs. TSMC also acquired a plant from E-Ton Solar Tech in the Southern Taiwan Science Park, which is currently being used as an intelligent warehouse.

Based on Innolux’s post-capital-reduction share capital of NTD 79.8 billion, the sale is expected to contribute around NTD 1.84 per share in earnings.

Read more

• [News] Innolux’s 4th Plant in Tainan Reportedly to be Secured by TSMC
• [News] Innolux Confirms Sale of Tainan Plant 4, with Micron & TSMC Reportedly in the Bidding Stage

(Photo credit: Innolux)