Amid the advancement of emerging applications such as Artificial Intelligence (AI), High-Performance Computing (HPC), data center, and autonomous vehicle, fan-out panel-level packaging (FOPLP) technology has successfully garnered industry attention due to its advantages in significantly improving computing power, reducing latency, and increasing bandwidth. As a result, more manufacturers are entering this field.

Recently, semiconductor equipment manufacturer ACM Research Shanghai introduced the Ultra ECP ap-p panel-level electroplating equipment for FOPLP.

Prior to this, ACM has launched the Ultra C vac-p negative pressure cleaning equipment designed for fan-out panel-level packaging applications, signaling that ACM has successfully entered the high-growth FOPLP market.

It is worth mentioning that since the second quarter of this year, chip manufacturers like AMD have actively approached TSMC and professional OSAT (Outsourced Semiconductor Assembly and Test) companies to promote chip packaging using FOPLP technology, further increasing industry focus on FOPLP.

In fact, advanced packaging has an increasing demand for low-latency, high-bandwidth, and cost-effective semiconductor chips, and FOPLP offers high bandwidth and high-density chip interconnects, making it a technology with higher potential.

FOPLP is a process performed on larger square substrates, allowing multiple chips, passive components, and interconnects to be integrated into a single package on a panel, offering greater flexibility, scalability, and cost effectiveness.

By redistributing chips on larger rectangular panels, FOPLP largely reduces the costs of packaging large GPU and high-density, high-bandwidth memory (HBM).

It is reported that the utilization rate of traditional silicon wafers is less than 85%, while that of panels exceeds 95%. The effective area of a 600×600 mm panel is 5.7 times that of a 300 mm traditional silicon wafer, with overall panel cost expected to decrease by 66%.

The increase in area utilization leads to higher capacity, greater flexibility in AI chip design, and significant cost reduction.

Currently, major players in the FOPLP advanced packaging field include Powertech Technology, ASE Group, SPIL, TSMC, Innolux, JSnepes, and Samsung Electro-Mechanics.

TrendForce points out that FOPLP technology presents advantages and disadvantages, facing both opportunities and challenges. Its main strengths are lower unit cost and larger package size, but as its technology and equipment systems are still developing, the commercialization process is highly uncertain.

It is estimated that the mass production timeline for FOPLP in consumer IC and AI GPU may fall between the second half of 2024 to 2026, and 2027-2028, respectively.

Read more

• [News] Innolux Targets to Begin FOPLP Mass Production by Year-End
• [News] TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road 

(Photo credit: ACMR)

According to a report by Nikkei, Japanese chip manufacturer Rapidus plans to establish a fully automated production line using robots and AI in northern Japan to produce 2nm chips for advanced AI applications, with mass production anticipated as early as 2027.

Reportedly, Rapidus claims that automated production will significantly accelerate production times, reducing chip delivery time to just one-third of that of its competitors. The company’s fab is expected to complete its external structure by October, with EUV lithography system set to arrive in December.

Compared to other companies already operating fabs, building a fully automated plant could give Rapidus a significant advantage. While the front-end of chip manufacturing are already highly automated, the back-end processes, such as packaging and testing, remain labor-intensive.

Rapidus CEO Atsuyoshi Koike stated that this approach will deliver higher performance and faster turnaround times for the same 2nm products compared to other competing chipmakers.

Per a report from Tom’s Hardware, Rapidus is currently two years behind TSMC and Samsung, both of which are expected to begin 2nm chip production in 2025. If Rapidus can deliver chips faster without compromising on price or quality, it may secure a place in the market.

Despite the optimistic outlook, Rapidus faces operational challenges. The company revealed that it will need JPY 2 trillion (approximately USD 14 billion) to begin operation in 2025, and at least JPY 5 trillion in total for the start of mass production.

Although Rapidus has received JPY 920 billion in subsidies from the Japanese government, private companies remain hesitant to invest due to the company’s lack of track record.

Atsuyoshi Koike added that, given the current situation, it is difficult for Rapidus to secure private financing. The company is discussing ways to make financing easier, such as implementing a government loan guarantee system.

Read more

• [News] Japanese Government Reportedly Plans to Offer Guaranteed Loans to Chip Startup Rapidus
• [News] Rapidus Partners RISC-V Player Esperanto, Targeting Low-Power AI Chip

(Photo credit: Rapidus)

According to sources cited in a report from Commercial Times, in response to the global increase in chip orders and rapid AI development, TSMC is actively seeking available land to keep its most advanced process technologies in Taiwan.

Currently, TSMC has already planned three 2nm fabs at the Nanzih Technology Industrial Park in Kaohsiung, southern Taiwan.

Regarding the need for additional land to accommodate facilities for more advanced nodes beyond 2nm, the report notes that the Kaohsiung City Government has been proactively preparing by evaluating land availability, as well as water and electricity supply, for TSMC’s next-generation advanced technology production, specifically targeting the A14 (14 angstrom) process.

Yet, regarding the matter, TSMC has remained discreet and declined to comment on market rumors regarding the progress of expansion.

Reportedly, the Nanzih Park site has the capacity to accommodate up to five fabs for TSMC, and there are rumors that its fourth and fifth fabs are likely to focus on A14 process, although TSMC has yet to confirm this.

TSMC’s first 2nm process fab in Nanzih is expected to begin mass production in 2025. Per sources cited by the report, the node will be used in high-performance computing (HPC), smartphones, electric vehicles, and autonomous driving applications.

Earlier, concerns were raised about the progress of TSMC’s CoWoS advanced packaging plant due to the discovery of cultural heritage sites at the Chiayi Science Park.

However, sources cited by Commercial Times have pointed out that while there have been some delays due to cultural heritage issues, TSMC’s adjustment plan has been approved. The company will adjust its working procedures in order to proceed with construction according to the original schedule, with no changes to the completion timeline.

Read more

• [News] Samsung Expected to Unveil its 1nm Plan in June, Advancing it to 2026
• [News] Decipher TSMC’s Calm Take on High-NA EUV Lithography Machines: Who May Have the Last Laugh in the Angstrom Era?

(Photo credit: TSMC)

In spite of its skyrocketing profit in Q2 thanks to the strong AI demand for memory chips, Samsung Electronics might be still struggling with losses in its foundry business, according to reports by ijiwei and Technews.

Citing Korean media, the reports indicate that Samsung’s foundry business is expected to face operating losses amounting to several trillion Korean won in 2024. The reports note that one of Samsung’s major challenges may lie in securing major foundry clients, as improving its yield rates and technologies in advanced nodes remains the company’s top priority.

Samsung posted better-than-expected revenue and profit numbers in Q2, as its revenue grew 23% YoY to 74.07 trillion won (USD 53.45 billion). Its operating profit, on the other hand, soared 1,462% YoY to 10.44 trillion won. However, the semiconductor giant didn’t disclose individual data for the foundry and LSI businesses respectively, but only providing the performance of the Device Solutions (DS) division as a whole.

In its press release, Samsung attributed the robust Q2 performance of its DS division to the market recovery driven by HBM, conventional DRAM and server SSDs. The move has brought up concerns on whether the foundry business is still grappling with losses.

The reports, citing Korean sources, indicate that Samsung’s semiconductor business (excluding the memory division) might have suffered a loss of nearly 300 billion won during the quarter. In addition, Samsung Securities predicts that the non-memory division recorded an operating loss as much as 457 billion won.

An earlier report by Business Korea noted that as the demand for 3nm has been rising, big techs, including NVIDIA, AMD, Qualcomm, MediaTek, Apple and Google, tend to allocate their orders to TSMC. Even Intel’s Lunar Lake, which is expected to make debut in September, is said to be manufactured with TSMC’s 3nm. The strong demand has reportedly prompted TSMC to raise the price of its 3nm process by over 20%.

Thus, the reports by ijiwei and Technews suggest that Samsung’s top priority would be to attract major clients for its foundry business. If Samsung can improve the yield rate of its 3nm GAA (Gate-All-Around) technology in a timely manner, it could potentially increase its order volume and market share by offering more competitive pricing.

On the other hand, the reports note that Samsung’s foundry business needs to shift its focus from the smartphone sector to the high-performance computing (HPC) segment, which means Samsung will need to apply technologies such as Backside Power Delivery Network (BSPDN) to enhance product performance and competitiveness. In response, Samsung plans to introduce BSPDN technology potentially ahead of schedule, aiming to boost its competitiveness when it begins mass production of its 2nm process technology in 2025.

Read more

• [News] Samsung to Intensify Efforts for Capturing Intel’s Advanced Packaging Orders Shifting from TSMC
• TrendForce: Top 10 Global Foundries at 4.3% QoQ Drop in 1Q24 Revenue as SMIC Climbed to 3rd Spot

(Photo credit: Samsung)

According to a report from Korea media outlet Yonhap News Agency, South Korea’s memory export to Taiwan has surged by 225% in the first half of the year.

The primary driver of this increase is reportedly due to South Korean chipmaker SK hynix’s supply of HBM to U.S. AI chip giant NVIDIA, which packages its AI accelerators at Taiwan’s TSMC.

A researcher at the Korea Institutes for Industrial Economics & Trade, Kim Yang-paeng, also noted that the sharp increase in exports is likely related to SK hynix’s supplies for TSMC’s final packaging of AI accelerators.

The report from Economic Daily News further highlights the strong momentum in NVIDIA’s AI chip shipments, with TSMC, as the key manufacturing partner, receiving steady advanced process orders.

The report from Yonhap News Agency also cited data from the industry ministry and the Korea International Trade Association released on August 11th, showing that South Korea’s memory exports to Taiwan in the first half of the year grew by 225.7% year-on-year, reaching USD 4.26 billion.

This growth significantly outpaces the overall increase in South Korea’s memory exports, which was 88.7%. Additionally, Taiwan has become South Korea’s third-largest market for memory exports in the first half of the year, climbing two spots to surpass Vietnam and the United States.

Another Korean media outlet, The Korea Herald, noted that since the 2010s, South Korea’s annual memory exports to Taiwan have ranged between USD 1 billion and 4 billion. The latest data indicates that this year’s export volume may set a new record, potentially reaching USD 8 billion.

Read more

• [News] SK hynix CEO: Demand for Memory Chips to Remain Robust until 1H25, Driven by HBM
• [News] Samsung’s 8-layer HBM3e to Start Mass Production in Q3, Driving HBM Sales to Soar 3-5 Times in 2H24

(Photo credit: SK hynix)