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Per a report from Reuters, Intel is said to be receiving the second new High-NA EUV equipment from ASML, costing EUR 350 million (~USD 383 million).
According to Intel’s earnings call on August 1, CEO Pat Gelsinger stated that Intel began receiving the first large equipment in December, and the installation process would take several months, which is expected to bring about a new generation of more powerful computer chip.
Gelsinger noted during the call that the second High-NA equipment is about to enter the facility in Oregon. Due to the poor stock performance following Intel’s earnings report, this statement did not attract much attention.
Previously, a senior executive from ASML once mentioned in July that the company already begun shipping the second High NA equipment to an unnamed customer, but would only record revenue for the first set this year. However, there are still some uncertainties regarding when the customer will adopt this equipment.
ASML has already received orders for over ten High-NA equipment from customers including TSMC, Samsung, Intel, Micron, and SK Hynix. Intel plans to use this technology for mass production by 2027, and TSMC is also set to receive the equipment this year, the time to put into production has not been disclosed, though.
ASML executive Christophe Fouquet stated on July 17 that DRAM memory chip manufacturers, which could refer to Samsung, SK Hynix, or Micron, are expected to start using High-NA equipment by 2025 or 2026.
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(Photo credit: ASML)
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Despite recent issues with NVIDIA’s GB200 shipments, the market remains optimistic about long-term AI demand, and CoWoS capacity continues to be in short supply.
According to a report from MoneyDJ, TSMC will assign orders of the initial stage of chip stacking in CoWoS packaging, Chip on Wafer (CoW), for the first time, to semiconductor assembly and test service provider SPIL.
The process will reportedly to manufactured at SPIL’s Zhong Ke Facility in Taichung. The company is said to build new capacity, with tool-in expected in the second quarter of 2025 and production ramping up in the third quarter.
TSMC President C.C. Wei previously disclosed that this year’s CoWoS capacity will more than double, with the growth trajectory similar in 2025. The company will continue to collaborate with OSATs to advance their packaging capabilities, Wei said.
Tien Wu, COO of another major outsourced semiconductor assembly & test services (OSAT) company ASE, also mentioned at its recent earnings call that the company has been co-developing both oS and CoW processes with their foundry partners for many years.
In fact, CoWoS is already a well-established technology. TSMC has been outsourcing the WoS (Wafer-on-Substrate) process, targeting small-batch, high-performance chips, while retaining the high-margin, high-tech CoW process in-house.
Lower-margin oS processes are handed over to packaging and testing companies. During the initial phase of this expansion wave, TSMC did not release CoW orders, but due to the overwhelming demand, they now have to outsource part of the process.
Industry sources cited by MoneyDJ further reveal that even Chinese companies have been excluded from the list, there are still several OSATs capable of handling TSMC’s outsourced CoWoS processes, such as Amkor, ASE, and SPIL.
After evaluation, SPIL’s plant in Central Taiwan was selected. It is reported that SPIL already collaborates with NVIDIA and AMD in the advanced packaging field, possessing capabilities not only for CoWoS-S but also for the higher-end CoWoS-L. This makes SPIL a strong second supplier for these major American companies.
Reportedly, TSMC will release the first phase of CoWoS-S orders to SPIL. Currently, SPIL’s CoWoS-related capacity is about 40,000 to 50,000 wafers per year. They plan to tool-in at the plant in Central Taiwan Science Park around the second quarter of next year.
It’s estimated by MoneyDJ’s report that TSMC’s CoWoS capacity remains in short supply, at 35,000 to 40,000 wafers per month this year. With the additional outsourced capacity, next year’s production could reach over 65,000 wafers per month, or possibly higher.
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(Photo credit: TSMC)
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According to a report from Nikkei on August 5, RS Technologies, a global giant in recycled wafers, has announced that due to increased orders, it will expand the monthly production capacity of its Japanese and Taiwanese plants to 580,000 wafers by 2024.
Despite the Japanese plant operating at full capacity, the company is still unable to meet the surging demand, prompting it to implement new investment plans to further increase production.
RS Technologies President Fang Yong Yi explained that there are various processes in semiconductor manufacturing, and many of them require repeated quality checks and testing, which utilize reclaimed wafers.
These reclaimed wafers are cleaned and subjected to precise regeneration processes, with each wafer being recyclable about 10 times. The company estimates that global monthly production output of reclaimed wafers will increase by 32% from 1.32 million in 2023 to 1.74 million in 2024.
Regarding TSMC’s new plant in Kumamoto Prefecture, which hints at a resurgence in semiconductor production within Japan, Fang noted that in 2023, orders for reclaimed wafers from major Japanese semiconductor companies like Kioxia significantly declined. However, in 2024, orders are expected to increase by 10,000 to 20,000 wafers month by month.
For 2024, the combined monthly production of RS Technologies’ Japanese and Taiwanese plants is projected to rise from 540,000 in 2023 to 580,000.
Reportedly, the Japanese plant is currently operating at full capacity with a 24-hour, three-shift system but still cannot meet demand. The plant’s current monthly production is 320,000 wafers, and new equipment investments are planned to add 170,000 wafers to the monthly capacity soon.
Fang further noted that orders for recycled test wafers from overseas vendors have also increased. New plants require a large volume of test wafers, and thus the simultaneous construction of new plants by overseas manufacturers represents a significant opportunity for the company.
RS Technologies, in a financial report released on May 13, announced plans to expand its overall monthly production capacity of reclaimed wafers to over 890,000 units by the end of 2026 to meet strong demand.
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As AI giant NVIDIA is said to delay its upcoming Blackwell series chips for months, which are now expected to hit the market around early 2025, the related semiconductor supply chain is experiencing a reshuffle. According to a report by the Korea Economic Daily, Samsung Electronics, which is eager to expand its market share for HBM3 and HBM3e, is likely to emerge as a major beneficiary in addition to AMD.
In March, NVIDIA introduced the Blackwell series, claiming it could enable customers to build and operate real-time generative AI on trillion-parameter large language models at up to 25 times less cost and energy consumption compared to its predecessor.
However, according to The Information, last week, NVIDIA informed major customers, including Google and Microsoft, that the shipments of its Blackwell AI accelerator would be delayed by at least three months due to design flaws.
Blackwell Delayed Potentially due to Design Flaws and TSMC’s Capacity Constraints
Tech media Overclocking points out that the defect is related to the part connecting the two GPUs, and creates problems for NVIDIA’s dual GPU versions, including the B200 and the GB200.
The delay has prompted tech companies to look for alternatives from NVIDIA’s competitors, such as AMD, according to the Korea Economic Daily. Microsoft and Google have already been working on next-generation products with AMD. For instance, Microsoft has purchased the MI300X, an AI accelerator from the US fabless semiconductor designer, the report says.
Samsung to Benefit thanks to the Collaboration with AMD
Samsung, as its HBM3 received AMD MI300 series certification in 1Q24, and is likely to provide HBM3e chips to AMD afterwards, is expected to benefit. Citing a semiconductor industry source, the Korea Economic Daily notes that as it is very risky for a single company to dominate the AI chip supply chain, the situation will create opportunities for Samsung and AMD.
It is also worth noting that Samsung’s HBM3 has passed NVIDIA’s qualification earlier, and would be used in the AI giant’s H20, which has been developed for the Chinese market in compliance with U.S. export controls.
According to TrendForce’s forecast in mid-July, the shipment share of AI servers equipped with self-developed ASIC chips in 2024 is expected to exceed 25%, while NVIDIA owning the lion’s share of 63.6%. AMD’s market share, on the other hand, is projected to reach 8.1% in 2024.
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(Photo credit: NVIDIA)
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According to a report from Economic Daily News, Innolux President James Yang announced on August 5 that the company is advancing its semiconductor fan-out panel-level packaging (FOPLP) with three key processes, targeting to enter mass production as soon as year-end.
The chip-first process technology, set to be the first to reach mass production by the end of this year, is expected to significantly contribute to revenue by the first quarter of next year.
Additionally, the RDL-first process, which target mid-to-high-end products, is anticipated to enter mass production within one to two years. The most technically challenging Through-Glass Via (TGV) process, being developed in collaboration with partners, will require another two to three years before it can be mass-produced.
At yesterday’s earnings call, there was significant interest in whether Innolux’s 4th Plant in Tainan (5.5-generation LCD panel plant) would be sold to Micron or TSMC.
Innolux Chairman Jim Hung stated that, in addition to quantifying the value of the sale, it is also important to consider the qualitative aspect, such as the potential new business opportunities that the deal could bring for both parties.
He further pointed out that while 5.5-generation plants are not the most competitive in the panel industry, they could still be valuable to other manufacturers. The sale of this asset is expected to contribute to Innolux’s non-operating income.
Regarding the recent focus on FOPLP (Fan-Out Panel-Level Packaging) mass production progress, Jim Hung emphasized that Innolux’s technology is already prepared.
James Yang explained that Innolux’s panel-level fan-out packaging technology will initially be applied to mid-to-low-end products, with plans to later expand into mid-to-high-end products.
He added that by entering the FOPLP field, Innolux aims for this technology to become a part of the AI PC industry, viewing the asset disposal as an opportunity to develop new business models and collaborations.
Previously reported by Economic Daily News, Innolux has been promoting the transformation of its fully depreciated old plants. The 3.5-generation line at the Tainan facility has been repurposed for advanced packaging with FOPLP, and the 4-generation line has been converted to produce X-ray sensors (through Raystar Optronics), both of which are related to semiconductor products.
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(Photo credit: Innolux)