South Korean media reports that the main suppliers of artificial intelligence (AI) chip packaging are concentrated in TSMC and ASE Technology Holding Co., which have been actively expanding production to meet the growing market demand. Despite efforts to develop technology and invest, South Korean companies like Samsung Electronics have not been able to narrow the gap with TSMC and ASE.

According to the Chosun Ilbo, industry insiders indicated that TSMC is expanding its advanced packaging (CoWoS) capacity by selecting a site in the southern region, while ASE also announced the construction of a second packaging and testing factory in California, USA, and plans to build another in Mexico. The rapid growth of the AI chip market highlights the increasing importance of semiconductor packaging and testing. As the benefits of semiconductor process miniaturization diminish and production costs rise, advanced packaging that can connect multiple components has become an ideal alternative solution. Some organizations predict that the semiconductor packaging market is expected to grow by more than 10% annually and expand to USD 90 billion by 2030.

Taiwanese companies like TSMC and ASE benefit a lot, almost monopolizing the contract manufacturing of AI chips for companies like NVIDIA and AMD. In terms of chip manufacturing, TSMC aims to double its CoWoS capacity from the previous year to meet increasing orders. TSMC recently announced plans to build two new advanced packaging factories in the southwest. The construction of the first factory was paused due to the discovery of ancient artifacts, but TSMC quickly sought a new site and announced an expansion of CoWoS facilities investment by 2025.

ASE, serving customers including Qualcomm, Intel and AMD, is also striving to increase equipment investment to meet rising orders. ASE, with the highest market share in the semiconductor packaging and testing field, is increasing its capacity and considering building a factory in Japan to match the growing demand. ASE’s CEO Wu Tianyu stated that they are looking for a location in Japan with a solid semiconductor ecosystem for the new factory.

Samsung has also announced packaging investment plans. The company intends to raise the investment in the new plant in Taylor, Texas, USA from USD 17 billion to more than USD 40 billion for the construction of an advanced packaging research and development center and facilities, in which it will allocate over KRW 2 trillion annually to expand advanced packaging production lines.

South Korean semiconductor back-end packaging and testing (OSAT) companies such as Hana Micron and Nepes are also striving for AI chip packaging orders based on technical development. Hana Micron, the leading OSAT company in South Korea, has announced its commitment to developing 2.5D AI semiconductor packaging. Nepes is developing Package on Package (PoP) technology, which integrates different semiconductors into one chip, with a target for commercial mass production in the second half of 2025.

Despite the efforts of South Korean companies, it is difficult to narrow the gap with Taiwanese companies in the short term. Taiwanese companies have actively developed advanced semiconductor packaging and commercializing CoWoS at a earlier time, while South Korean packaging companies lag in accumulated technologies. South Korean industry insiders point out that TSMC and ASE have been collaborating for over 30 years. Therefore, as TSMC secured a large number of AI chip orders, it would prove a boon to Taiwan’s packaging ecosystem. In contrast, South Korea’s packaging industry, which has long focused on the memory production market, still has a long way to go to expand its market and even compete with Taiwanese companies.

Google’s Tensor G4 could mark Samsung’s last mass-produced SoC, as earlier in May, Tensor G5 is reportedly adopting TSMC’s advanced 3nm process. Now here’s the latest development. According to a report by Wccftech, the chip, to be used in Google’s upcoming Pixel 10 lineup, has already reached tape-out, with mass production expected in 2025.

Google’s Tensor G5 would be its first fully self-designed smartphone SoC. Previous Tensor chips, somehow, were modifications from Samsung’s Exynos series, with Samsung being its foundry partner.

The report stated that Google’s decision to collaborate with TSMC is influenced by the Taiwanese semiconductor company’s established reliability in mass-producing wafers using its next-generation nodes.

Before Google, the foundry behemoth has already secured several major clients for its 3nm node. Both Qualcomm and Taiwanese smartphone fabless company MediaTek have reportedly adopted TSMC’s N3E node for their first 3nm chipsets. Apple’s upcoming A18 chips for iPhone 16 models, are said to be manufactured with TSMC’s N3E node as well, according to a report by Commercial Times.

On the other hand, regarding the progress of 3nm, Samsung is still struggling with the low yield rate for its latest Exynos 2500 processors. The company targets to increase the yield rate to over 60% before the product enters mass production, according to a previous report by Korean media outlet ZDNet Korea.

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• [News] Google Reportedly Shifts Orders from Samsung to TSMC for Its Upcoming Tensor G5 in the Pixel 10 Series

(Photo credit: Google)

According to a report from Notebookcheck citing market rumors, it’s suggested that the AMD Zen 6 architecture, codenamed Morpheus, will utilize 2nm and 3nm processes. The Zen 6 series includes three versions: Standard, Dense Classic, and Client Dense. Later rumors also indicate the architecture will feature three core configurations: 8-core (Zen 6), 16-core (Zen 6c), and 32-core (Zen 6c Extended).

The same report further indicates that, in the consumer market, the Zen 6 series will include high-end laptop versions like Medusa Point, platform versions for AM5 like Medusa Ridge, and versions suitable for both gaming laptops and desktops like Medusa Halo. AMD plans to launch the Zen 6 architecture in the second quarter of 2025, with production starting by the end of 2025, though mass production might be delayed to 2026.

AMD unveiled Strix Point at COMPUTEX 2024, featuring a combination of the Zen 5 series and RDNA 3.5 architecture. Strix Point’s launch was delayed by two quarters due to issues related to AMD’s plans for 3nm production, which were eventually canceled.

AMD also had plans for Strix Halo, rumored to use TSMC’s N3E process for producing IOD (input/output die) chips similar to Medusa Halo. Strix Halo’s launch was also delayed, possibly due to issues with the IOD chip.

Compared to the Zen 5 series architecture, the Zen 6 series is expected to feature a nearly redesigned memory controller and a new scheduling program. The Zen 6 architecture represents a significant overhaul similar to the Zen 2 architecture, with substantial changes. AMD is said to be looking to finalize the Zen 6 series design by the third quarter and commence production in 2025.

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• [News] A Quick Overview at TSMC’s Latest Collaboration with Intel, NVIDIA and AMD at COMPUTEX 2024
• [News] TSMC’s Advanced Packaging Capacity Fully Booked by NVIDIA and AMD Through Next Year

(Photo credit: AMD)

According to a report from Economic Daily News, TSMC’s advanced packaging platform SoIC is said to have secured another heavyweight customer, with Apple expected to adopt the technology in 2025. If confirmed, Apple will join AMD as a major client expanding its use of TSMC’s SoIC .

TSMC has categorized advanced packaging under its 3D Fabric system integration platform, which comprises three main parts: the SoIC series for 3D silicon stacking technology, and the CoWoS and InFo families for back-end advanced packaging.

Reportedly, it is said that the CoWoS family has been facing capacity constraints recently. To address this, TSMC is not only expanding its own production but also collaborating with testing service providers to increase output.

On the other hand, TSMC’s SoIC platform, which is part of front-end packaging, has fewer bottlenecks and began small-scale production in 2022. TSMC has long-term plans to expand SoIC capacity by more than 20 times by 2026 to meet growing customer demand.

In recent years, NVIDIA and AMD have been aggressively targeting the AI market, setting high growth targets for 2024. Both companies have sought collaboration with TSMC and several Taiwanese supply chain partners. The key advantage is Taiwan’s comprehensive supply chain, which can accelerate innovation. As TSMC’s advanced packaging capacity ramps up, industry analysts are optimistic that this will facilitate the smooth procurement and delivery of critical components.

In the highly anticipated SoIC area, AMD’s MI300 series is a recent story of deepened collaboration with TSMC. According to information from AMD and TSMC’s technology forum, the MI300 series not only uses TSMC’s 5nm process but also integrates multiple technologies from TSMC’s 3DFabric platform. This includes stacking the 5nm GPU and CPU on a base chip using SoIC-X technology and further integrating them into CoWoS packaging.

Beyond AMD’s adoption, the same report has cited rumors that Apple might adopt this technology in 2025.

Although TSMC consistently refrains from commenting on individual client details, industry speculation has long suggested that Apple intends to incorporate related technology into the next-generation M-series chips, and possibly even the A-series processors. This could significantly increase transistor density, driving the next wave of innovation in the mobile device and AI PC markets.

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• [News] TSMC Reportedly Secures 4 Major Clients for SoIC, Including Apple, NVIDIA and Broadcom
• [News] TSMC’s SoIC Demand Heats Up, Reports Suggest Significant Capacity Expansion

(Photo credit: TSMC)

As semiconductor manufacturing enters the Angstrom Era, there have been significant adjustments in architecture and circuit design. To free up more surface area on chips, moving power delivery to the backside has become a mainstream consensus, making the Backside Power Delivery Network (BSPDN) the premier solution in advanced manufacturing.

According to a report from Commercial Times, regarding BSPDN, leading companies such as TSMC, Intel, and imec (Belgian Microelectronics Research Center) have proposed different approaches focusing on wafer thinning, atomic layer deposition (ALD) inspection, and wafer regeneration solutions, with mass production starting from 2026, benefiting supply chains.

Among them, TSMC’s Super Power Rail is considered direct and effective, albeit complex and expensive to implement. To reflect its value, TSMC has adjusted its pricing strategy. According to the report, the foundry leader has successfully raised prices for advanced processes, with further increases slated for January 1 next year, particularly targeting the 3/5-nanometer AI product lines with adjustments ranging from 5% to 10%.

Industry sources cited by the same report point out that there are several technological breakthroughs in backside power delivery. One critical aspect involves polishing the wafer backside to a thickness close enough for transistor contact. However, this process significantly compromises the wafer’s rigidity. Therefore, after front-side polishing, it’s essential to bond a carrier wafer to support the backside manufacturing process.

Additionally, technologies like nano Through-Silicon Vias (nTSV) require more equipment for ensuring uniform copper metal deposition within nano-scale holes.

Therefore, leading companies have proposed different approaches focusing on wafer thinning, atomic layer deposition (ALD) inspection, and wafer regeneration solutions. This development is benefiting related supply chain entities such as Kinik Company, Skytech, and Phoenix Silicon International Corporation.

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• [News] How Costly is the High-NA EUV? TSMC Reportedly Shocked, Considering Not Using the Equipment in its A16 Node
• [News] EUV as a Strategic Asset in the Most Advanced Processes: Progress in Intel/TSMC/Samsung’s Adoptions

(Photo credit: TSMC)