According to a report from Korean media outlet ZDNet Korea, the yield rate for Samsung Electronics’ latest Exynos 2500 processor has improved to slightly below 20% from single digits in the first quarter. However, the current yield rate is still said to be falling short of mass production standards. It remains uncertain whether it can be used in the flagship Galaxy S25 series smartphones in the future.

The report further indicates that this yield rate is still insufficient for mass production, which typically requires yields to be increased to over 60%. Therefore, Samsung Electronics’ System LSI department reportedly plans to work on improving the yield rate of the Exynos 2500 processor in the second half of this year.

The report states that it is still uncertain whether the Exynos 2500 processor can be used in the future Galaxy S25 series flagship smartphones. Since there is still considerable time before the official launch of the Galaxy S25 series, Samsung hopes to improve the yield rate of the Exynos 2500 processor to 60% by October this year.

On the other hand, TSMC is overwhelmed with 3nm orders, with major companies like Apple, NVIDIA, AMD, Qualcomm, Intel, and MediaTek all utilizing TSMC’s 3nm process. Per a report from TechNews, during TSMC’s technology forum on May 23, the 3nm production capacity this year has more than tripled compared to last year, but this is actually still not enough, so efforts are still being made to meet customer demand.

Read more

• [News] Major Clients Reportedly Fully Allocate TSMC’s Production Capacity Until 2026, 3nm Process in High Demand
• [News] Samsung Reportedly to Challenge Apple/TSMC with 3nm Exynos W1000

(Photo credit: Samsung)

According to a report by the Economic Daily News, TSMC has secured another AI business opportunity. Following its exclusive contract manufacturing of AI chips for tech giants such as NVIDIA and AMD, TSMC, in collaboration with its subsidiary, the ASIC design service provider Global Unichip Corporation (GUC), has reportedly made significant progress in producing essential peripheral components for AI servers, specifically high-bandwidth memory (HBM). Together, they have secured a major order for the foundational base die chips of next-generation HBM4.

TSMC and GUC typically do not comment on order details. SK Hynix, on the other hand,  has clarified in a press release to Bloomberg that it has not signed a contract with GUC for its next-generation AI memory chips, according to the Economic Daily News.

Industry sources cited by the report point out that the strong demand for AI is not only making high-performance computing (HPC) related chips highly sought after, but also driving robust demand for HBM, creating new market opportunities. This surge in demand has attracted major memory manufacturers such as SK Hynix, Samsung, and Micron to actively invest. Under the influence of AI engines, the current production capacity for HBM3 and HBM3e is in a state of supply shortage.

As AI chip manufacturing advances to the 3nm generation next year, the existing HBM3 and HBM3e, limited by capacity and speed constraints, may prevent the new generation of AI chips from reaching their maximum computational power. Consequently, the three major memory manufacturers are unanimously increasing their capital expenditures and starting to invest in the development of next-generation HBM4 products, aiming for mass production by the end of 2025 and large-scale shipments by 2026.

While memory manufacturers are delving into the research and development of next-generation HBM4, the semiconductor standardization organization JEDEC Solid State Technology Association is also busy establishing new standards related to HBM4. It’s also rumored that JEDEC will relax the stacking height limit for HBM4 to 775 micrometers, hinting that the previously required advanced packaging technology using hybrid bonding can be postponed until the next generation of HBM specifications.

Industry sources cited by the report also suggest that the most significant change in HBM4, besides increasing the stacking height to 16 layers of DRAM, will be the addition of a logic IC at the base to enhance bandwidth transmission speed. This logic IC, known as the base die, is expected to be the major innovation in the new generation of HBM4 and possibly a reason for JEDEC’s relaxation of the stacking height limitation.

On the other hand, SK Hynix has announced its collaboration with TSMC to advance HBM4 and capture opportunities in advanced packaging. Industry sources also indicate that GUC has successfully secured the critical design order for SK Hynix’s HBM4 base die.

The design is expected to be finalized as early as next year, with production to be carried out using TSMC’s 12nm and 5nm processes, depending on whether high performance or low power consumption is prioritized.

Reportedly, it’s suggested that SK Hynix’s decision to entrust the base die chip orders to GUC and TSMC is primarily because TSMC currently dominates over 90% of the CoWoS advanced packaging market used in HPC chips.

Read more

• [News] SK Hynix Disclosed Details Regarding HBM4e, Reportedly Integrating Computing and Caching Functionalities
• [News] SK Hynix Partners with TSMC to Strengthen HBM Technological Leadership

(Photo credit: TSMC)

SK keyfoundry, a subsidiary of memory giant SK hynix, has achieved notable progress in the development of Gallium Nitride (GaN) power semiconductors. According to the latest report by Business Korea, the foundry would begin producing power semiconductors for Tesla in the second half of 2024.

According to the report, SK keyfoundry announced in early June that it has achieved the primary device characteristics of a 650V GaN High Electron Mobility Transistor (HEMT), which surpasses traditional silicon-based semiconductors in both efficiency and durability. This advancement aligns with SK keyfoundry’s plan to finalize the development of GaN power semiconductors by the end of this year.

It is worth noting that TSMC has also entered the GaN market a few years ago, as it provides GaN process for manufacturing 100/650V discrete GaN power devices for customers. For instance, in 2020, the world’s largest foundry has announced to collaborate with STMicroelectronics. According to its press release, ST’s GaN products will be manufactured using TSMC’s leading GaN process technology, including applications relating to automotive converters and chargers for hybrid and electric vehicles.

Regarding the development of SK keyfoundry, Business Korea noted that the company established an official team in 2022 to focus on the development of GaN technologies. Citing industry sources on June 20^th, the report stated that SK keyfoundry will reportedly begin producing power semiconductors for Tesla in the second half of this year.

Moreover, it also mulls to broaden its business scope, entering markets like fast-charging adapters, data centers, and energy storage systems afterwards. Starting in November, the company plans to manufacture power management chips (PMIC) at its 8-inch wafer fab in Cheongju.

Though foundries have not significantly contributed to SK hynix’s revenue so far, the development of power semiconductors could boost overall foundry sales. According to the report, SK keyfoundry also provides contract manufacturing for non-memory semiconductors such as Display Driver ICs (DDI) and Microcontroller Units (MCU), further diversifying its product lineup.

In the current landscape of the new energy market, third-generation semiconductors such as SiC and GaN have gained significant traction. SiC (Silicon Carbide) and GaN could offer significant benefits over traditional silicon.

To elaborate, semiconductor materials have the so-called “bandgap,” an energy range in a solid where no electrons can exist. According to German chipmaker Infineon, GaN has a bandgap of 3.4 eV, compared to silicon’s 1.12 eV bandgap. The wider bandgap of GaN allows it to sustain higher voltages and temperatures than silicon. While SiC dominates the high-power domain, GaN excels at lower power levels, offering lower conduction losses.

Read more

• [News] Infineon in GaN and SiC Expansion Drive Advancements in the New Energy Market

(Photo credit: SK keyfoundry)

According to a previous report from Nikkei citing sources, TSMC is rumored to be entering the fan-out panel-level packaging sector. As cited in a report from UDN, Intel and Samsung have also announced plans to invest in this area. With TSMC, the leading wafer foundry, joining the fray, the three semiconductor giants are set to compete in fan-out panel-level packaging.

TSMC stated yesterday that the company is closely monitoring the progress and development of advanced packaging technologies, including panel-level packaging technology.

Nikkei reported that in response to future AI demand trends, TSMC is collaborating with equipment and material suppliers to develop new advanced chip packaging technology. This technology uses a rectangular substrate for packaging, replacing the current traditional circular wafer, to accommodate more chipsets on a single wafer. The report further mentioned that TSMC’s research is still in its early stages and might take several years to commercialize, but it represents a significant technological shift.

Reportedly, TSMC previously considered the challenge of using rectangular substrates to be too high, requiring substantial time and effort from both the company and its suppliers, along with upgrades or replacements of many production tools and materials.

Nikkei  also mentioned that TSMC is currently experimenting with rectangular substrates measuring 515 mm in length and 510 mm in width, providing more than three times the usable area of a 12-inch wafer.

TSMC is expanding its advanced chip packaging capacity, with the expansion of the Taichung plant mainly for NVIDIA, while the Tainan plant is primarily for Amazon and its chip design partner Alchip Technologies.

TSMC’s CoWoS advanced chip packaging can combine two sets of NVIDIA Blackwell GPU chips and eight sets of high-bandwidth memory (HBM). As single chips need to accommodate more transistors and integrate more memory, the mainstream 12-inch wafer might not be sufficient for packaging advanced chips in two years.

Samsung and Intel have also recognized the aforementioned issues and are investing in next-generation advanced packaging technologies.

Samsung currently offers advanced packaging services such as I-Cube 2.5D packaging, X-Cube 3D IC packaging, and 2D FOPKG packaging. For applications requiring low-power memory integration, such as mobile phones or wearable devices, Samsung already provides platforms like fan-out panel-level packaging and fan-out wafer-level packaging.

Intel is planning to launch the industry’s first glass substrate solution for next-generation advanced packaging, with mass production scheduled between 2026 and 2030. Intel anticipates that data centers, AI, and graphics processing—markets that require larger volume packaging and higher-speed applications and workloads—will be the first to adopt this technology.

Read more

• [News] TSMC Reportedly Develops Panel-Level Packaging, Another New Chip Packaging Tech
• [News] Samsung Reportedly Targets Q4 Trial Production of SiP Glass Substrate, Competing with Intel in the Advanced Packaging Market

(Photo credit: Intel)

According to a report from Nikkei citing sources, TSMC is developing a new advanced chip packaging technology that uses rectangular panel-like substrates, rather than the traditional circular wafers currently in use.

This technology allows for more chips to be placed on a single substrate, addressing the future demand trends driven by AI. Although the research is still in its early stages and may take several years to reach mass production, it represents a significant technological shift for TSMC, the report notes.

Reportedly, TSMC is currently experimenting with rectangular substrates measuring 515 mm by 510 mm, providing more than three times the usable area compared to the current 12-inch wafers, and therefore can better suit the demand for AI chipsets.

In response to Nikkei’s inquiry, TSMC stated that the company is closely monitoring advancements and developments in advanced packaging technologies, including panel-level packaging.

Read more

• [News] TSMC Advanced Packaging Crucial for AI Computing Power

(Photo credit: TSMC)