According to a report by the Korean media outlet The Chosun Daily on June 16th, Samsung’s “Galaxy Tab S10” series tablets will be equipped with MediaTek’s Dimensity 9300+ application processor (AP) from Taiwan, marking the first instance of MediaTek’s AP being adopted by Samsung’s flagship tablet.

The report highlights that MediaTek’s APs have primarily been used in Samsung’s mid-to-low-end smartphones. The decision to use MediaTek’s AP in the Galaxy Tab S10 series, instead of Qualcomm’s or Samsung’s own APs, is a significant shift for Samsung.

The sources cited in the report believe that Samsung’s move is a butterfly effect caused by TSMC’s price hikes. TSMC’s price increases have potentially led to a rise in the cost of Qualcomm’s Snapdragon chips, which are manufactured by TSMC. After price negotiations, Samsung’s Mobile Communications Business (MX) decided to equip the Snapdragon 8 Gen 3 chips only in the Galaxy Tab S10 Ultra series, while using MediaTek’s Dimensity chips in the Plus and base models.

The same report further indicates that from Samsung’s perspective, choosing Dimensity to reduce costs and diversify the supply chain is a sensible decision. However, for Samsung’s foundry division which manufactures Exynos, this development is somehow unwelcome. While Exynos used to have price advantages over Snapdragon in supplying Samsung’s flagship products, the use of Dimensity jeopardizes Exynos’ competitive edge in its bargaining power for future flagship product pricing negotiations.

Samsung Electronics’ upcoming AP, the “Exynos 2500,” set for release next year, will also face similar challenges. With TSMC recently rumored to increase price for its 3nm process, costs for Qualcomm’s Snapdragon 8 Gen 4, slated for release in October, are expected to sharply increase. Industry source cited by the report further suggests the cost of this chip could rise from over USD 200 in the previous generation to more than USD 250.

TSMC Chairman C.C. Wei recently stated that, almost all companies interested in AI-related demand are willing to work with TSMC. From the yield rates obtained by customers, TSMC offers the best cost-effectiveness solutions, hence there is room for price increases. Per a report from Liberty Times, the wafer order prices for TSMC in 2025 are expected to be finalized in September and October this year.

Read more

• [News] Samsung Reportedly to Challenge Apple/TSMC with 3nm Exynos W1000
• [News] MediaTek Announces 4nm Dimensity 7300 Series Chips, Supporting Foldable Devices

(Photo credit: MediaTek)

In 2023, Samsung disclosed plans to launch its advanced three-dimensional (3D) chip packaging technology, which would be able to integrate memory and processors needed for high-performance chips, in much smaller sizes. Now, at the Samsung Foundry Forum in San Jose taken place in June, the tech giant made it public that it would introduce 3D packaging services for HBM within this year, according to the latest report by The Korea Economic Daily.

For now, HBM chips are predominantly packaged with 2.5D technology. Citing industry sources as well as personnel from Samsung, the company’s 3D chip packaging technology is expected to hit the market for HBM4, the sixth generation of the HBM family.

Samsung’s announcement regarding its 3D HBM packaing roadmap has been made after NVIDIA CEO Jensen Huang revealed Rubin at COMPUTEX 2024, the company’s upcoming architecture of its AI platform after Blackwell. The Rubin GPU will reportedly feature 8 HBM4, while the Rubin Ultra GPU will come with 12 HBM4 chips, targeting to be released in 2026.

Currently, Samsung’s SAINT (Samsung Advanced Interconnect Technology) platform includes three types of 3D stacking technologies: SAINT S, SAINT L, and SAINT D.

SAINT S involves vertically stacking SRAM on logic chips such as CPUs, while SAINT L involves stacking logic chips on top of other logic chips or application processors (APs). SAINT D, on the other hand, entails vertical stacking of DRAM with logic chips like CPUs and GPUs.

The Korea Economic Daily noted that unlike 2.5D technology, under which HBM chips are horizontally connected with a GPU on a silicon interposer, by stacking HBM chips vertically on top of a GPU, 3D packaging could further accelerate data learning and inference processing, and thus does not require a silicon interposer, a thin substrate that sits between chips to allow them to communicate and work together.

It is also understood that Samsung plans to offer 3D HBM packaging on a turnkey basis, according to the Korea Economic Daily. To achieve this, its advanced packaging team will vertically interconnect HBM chips produced by its memory business division, with GPUs assembled for fabless companies by its foundry unit, the report noted.

Regarding Samsung’s long-time rival, TSMC, the company’s Chip on Wafer on Substrate (CoWoS) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and HBM stacks side by side on one interposer. TSMC also made similar announcement in May, reportedly utilizing 12nm and 5nm process nodes in manufacturing HBM4, according to a report by AnandTech.

Read more

• [News] TSMC Reportedly Prepares Next-generation HBM4 Manufacturing, Utilizing 12nm and 5nm Process
• [News] Samsung Accelerates 3D Packaging with Hybrid Bonding Production Line in Korean Advanced Packaging Hub

(Photo credit: Samsung)

Taiwan’s semiconductor giant, TSMC, faces overwhelming demand for its 3nm technology, with major clients like Apple and NVIDIA fully allocate its production capacity.

According to a report from Commercial Times, orders are expected to be filled through 2026. Reportedly, TSMC is planning to raise its 3nm prices by over 5%, and advanced packaging prices are anticipated to increase by approximately 10% to 20% next year.

The members of TSMC’s 3nm family include N3, N3E, N3P, as well as N3X and N3A. As the existing N3 technology continues to be upgraded, N3E, which began mass production in the fourth quarter of last year, targets applications such as AI accelerators, high-end smartphones, and data centers.

N3P is scheduled for mass production in the second half of this year and is expected to become mainstream for applications in mobile devices, consumer products, base stations, and networking through 2026. N3X and N3A are customized for high-performance computing and automotive clients.

Source: TSMC

Per the industry sources cited by the same report, TSMC’s Zhunan advanced packaging plant (AP6), operational for a year now, has become Taiwan’s largest CoWoS base with the equipment moved into its AP6C plant. In the third quarter, CoWoS monthly production capacity is expected to double from 17,000 to 33,000 wafers.

Industry sources cited by the report further suggests that while AI accelerators do not use the most cutting-edge manufacturing processes, they rely heavily on advanced packaging technology. The ability of global semiconductor companies to secure more advanced packaging capacity from TSMC will determine their market penetration and control.

TSMC’s advanced packaging capacity is scarce, with primary customer NVIDIA having the highest demand, occupying about half of the capacity, followed closely by AMD. Broadcom, Amazon, and Marvell have also expressed strong interest in using advanced packaging processes. With gross margins close to 80%, NVIDIA is said to agree to price increases to secure more advanced packaging capacity, thereby distancing itself from competitors.

Previously, NVIDIA CEO Jensen Huang emphasized that TSMC is not just manufacturing wafers but also handling numerous supply chain issues. He also agreed that the current pricing is too low and would support TSMC’s price increase actions.

The industry sources cited by Commercial Times have indicated that TSMC plans to add CoWoS-related equipment by the third quarter and has requested equipment manufacturers to dispatch more engineers to fully staff its Longtan AP3, Zhunan AP6, and Central Taiwan Science Park AP5 plants.

In addition to Zhunan’s AP6C, the Central Taiwan Science Park plant, which originally only handled the latter stages of oS, will also gradually transition to CoW processes. Meanwhile, the Chiayi site is in the land preparation stage and is expected to progress faster than Tongluo.

Reportedly, industry sources further reveal that the prices for advanced process nodes such as 3nm and 5nm will also be adjusted. Particularly, strong demand for 3nm orders in the second half of the year is expected to drive utilization rates to near full capacity, extending through 2025. The 5nm process is experiencing similar demand dynamics, driven by AI needs.

Read more

• [News] Major Clients Reportedly Fully Allocate TSMC’s Production Capacity Until 2026, 3nm Process in High Demand
• [News] NVIDIA CEO Jensen Huang Supports C.C. Wei’s Theory and Backs for TSMC to Increase Price

(Photo credit: TSMC)

With the United States expected to further restrict China from acquiring advanced GAA (Gate-All-Around) chip architecture capabilities, coupled with reports of poor yield rates in Samsung’s 3nm GAA generation, the semiconductor industry sources cited in a report from Commercial Times state that TSMC’s 3nm FinFET process is enjoying dominance. Reportedly, due to the high demand and limited supply capacity, upstream IC design companies are beginning to report price hikes.

Seven global tech giants, including NVIDIA, AMD, Intel, Qualcomm, MediaTek, Apple, and Google, are set to gradually adopt TSMC’s 3nm process. As per the sources cited in the report from Commercial Times, Qualcomm’s Snapdragon 8 Gen 4, built using TSMC’s N3E process, has seen a price increase of 25% compared to the previous generation, potentially triggering a subsequent trend of price hikes.

Samsung was the first to commence mass production of 3nm chips using the GAA process in June 2022. However, the first-generation N3 node, SF3E, did not achieve significant success and was initially limited to cryptocurrency applications. Subsequently, the yield rate for its own Exynos 2500 chip also fell short of expectations.

Additionally, Google’s Tensor processors, which are manufactured by Samsung, still use Samsung’s 4nm process in their fourth generation. However, it is said in the report that the fifth generation will switch to TSMC’s 3nm process.

In the second half of the year, numerous AI products will be launched in the consumer market. Among the three major players in the mobile chip market, Qualcomm’s Snapdragon 8 Gen 4, MediaTek’s Dimensity 9400, and Apple’s A18 and M4 series will all be built using TSMC’s N3 family. Moreover, Google’s Tensor G5 will also compete in the market.

It is rumored that Qualcomm’s Snapdragon 8 Gen 4 has already initiated the first wave of price increases. The industry sources cited in the report claim that the procurement cost of mobile chips was already high, with last year’s flagship 8 Gen 3 costing around USD 200. This year’s flagship chip might exceed USD 250. Whether competitors will follow suit remains to be seen.

However, industry sources cited by the report also point out that the price increase is within a reasonable range. Compared to the 5nm process, the cost per wafer for the 3nm process is about 25% higher. This increase does not yet take into account overall wafer quantities and design architecture factors.

TSMC President C.C. Wei has also revealed that TSMC products are highly power-efficient and have better yield rates. When considering the cost per chip, TSMC is the most cost-effective.

Read more

• [News] Major Clients Reportedly Fully Allocate TSMC’s Production Capacity Until 2026, 3nm Process in High Demand
• [News] NVIDIA CEO Jensen Huang Supports C.C. Wei’s Theory and Backs for TSMC to Increase Price

(Photo credit: TSMC)

With high demand for AI chips from major players like NVIDIA and AMD, the capacity for advanced packaging falls short of meeting demand. Industry sources cited in a report from the Economic Daily News indicate that TSMC’s new CoWoS facility in the Southern Taiwan Science Park in Chiayi is now undergoing environmental impact assessments, prompting the commencement of equipment procurement.

Additionally, considering the insufficiency of planned CoWoS facilities in the Chiayi park, TSMC is reportedly sending representatives to survey additional land for potential expansion.

Regarding these developments, TSMC stated on June 11 that they do not comment on market rumors.

With the rapid development of AI applications, the demand for advanced packaging in the chip market has surged. TSMC, serving as the major foundry partner for tech giants like NVIDIA and AMD in AI chip production, has faced continuous high demand for advanced packaging capacity for some time. The company has been actively expanding related capacity and is now venturing into building a new CoWoS facility in the Southern Taiwan Science Park in Chiayi.

According to the information previously announced by the Chiayi County government, TSMC’s advanced packaging facility will occupy approximately 20 hectares in the Southern Taiwan Science Park, with the first facility covering around 12 hectares. The first advanced packaging fab is expected to be completed by the end of 2026, creating 3,000 job opportunities. TSMC initially plans to build two advanced packaging facilities in the area.

According to official information from TSMC, its backend test and packaging facilities include the Hsinchu Advanced Backend Fab 1, Southern Taiwan Science Park Advanced Backend Fab 2, Longtan Advanced Backend Fab 3, Central Taiwan Science Park Backend Advanced Fab 5, and Miaoli Zhunan Advanced Backend Fab 6.

Industry sources cited by the same report from the Economic Daily News further indicate that advanced packaging-related equipment is currently being gradually supplied to TSMC’s Zhunan, Central Taiwan, and Southern Taiwan fabs, with shipments to the Chiayi facility expected to commence from the third quarter of next year.

TSMC Chairman C.C. Wei previously mentioned that despite their efforts to increase capacity, the strong demand from customers has led to an insufficient supply, which has led to outsourcing to specialized packaging and testing foundries. He emphasized TSMC’s ongoing expansion of CoWoS advanced packaging capacity, with the goal of doubling their in-house capacity growth this year and continuing efforts into next year to narrow the gap between supply and demand.

TSMC has integrated its advanced packaging-related technologies into the “3DFabric” platform, allowing customers to select and configure according to their needs. The front-end technologies include System on Integrated Chip (SoIC), while the back-end assembly and testing technologies include Integrated Fan-Out (InFO) and the CoWoS series family.

In June 2023, TSMC announced the official opening of its Advanced Backend Fab 6 located in the Zhunan Science Park, becoming its first fully automated advanced packaging and testing facility to realize integrated front-end to back-end processes and testing services under the 3DFabric platform.

Source: TSMC

Read more

• [News] Major Clients Reportedly Fully Allocate TSMC’s Production Capacity Until 2026, 3nm Process in High Demand
• [News] NVIDIA CEO Jensen Huang Supports C.C. Wei’s Theory and Backs for TSMC to Increase Price

(Photo credit: TSMC)