Fab inventories have declined for two consecutive quarters, indicating that reducing excess stock may currently be the semiconductor industry’s top priority. According to industry sources cited in a report from Commercial Times, fabs are predicted to wait until the second half of 2024 to resume ordering silicon wafers.

According to the latest quarterly analysis report from SEMI, a major microelectronics association, global silicon wafer shipments in the first quarter of 2024 reached 2,834 million square inches (MSI), marking a 5.4% decrease from the previous quarter and a 13.2% decrease from the same period last year.

SEMI attributes this decline in silicon wafer shipments to the continuing decline in IC fab utilization and inventory adjustments. Consequently, shipments of silicon wafers of all sizes experienced negative growth in the first quarter of 2024.

Industry sources cited by the same report note that, based on recent trends in foundry orders, apart from TSMC, other semiconductor manufacturers have seen capacity utilization rates around 70%. Among these, DRAM and Flash memory wafer shipments have shown year-on-year increases of 20.3% and 1%, respectively, indicating better performance compared to previous periods.

Japanese silicon wafer manufacturer Sumco recently announced in its financial report that in the first quarter, overall demand for 12-inch silicon wafers had bottomed out. Demand for logic chips used in AI and DRAM had increased. However, for applications outside of AI, customers continued to adjust their production.

Sumco estimates that due to customer production adjustments and the recovery of silicon wafer demand, it may take until the second half of 2024 for the situation to improve.

Industry sources cited by Economic Daily News believe that most IC design companies have returned to normal days of inventory (DOI) and are prioritizing urgent orders for foundries. However, the inventory levels of fabs and memory fabs remain historically high, so they will primarily focus on digesting existing long-term contracts (LTA) in the short term.

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(Photo credit: TSMC)

As the demands for AI and HPC processors keep their momentum, driving the usage of advanced packaging technologies, TSMC revealed plans to further expand its chip-on-wafer-on-substrate (CoWoS) capacity at a compound annual rate (CAGR) of over 60% until at least 2026, according to a report by AnandTech.

According to its latest roadmap revealed at the company’s European Technology Symposium earlier, TSMC would now be able to more than quadruple its CoWoS capacity from 2023 levels by the end of 2026, the report indicated.

Last year, the foundry leader announced plans to more than double its CoWoS capacity by the end of 2024, but now it needs to be more ambitious, not only to meet existing demand but also address the future market.

TSMC is also preparing additional versions of CoWoS (specifically CoWoS-L) to support building system-in-packages (SiPs) with up to eight reticle sizes, just in case that increasing CoWoS capacity four-fold over three years may still be insufficient, the report said.

In addition to CoWoS, TSMC also plans to expand its system-on-integrated chips (SoIC) capacity at a CAGR of 100% through 2026, indicating that its SoIC capacity will increase eight-fold from 2023 levels by the end of 2026, according to AnandTech.

When it comes to the latest overseas expansion plans regarding major Taiwanese foundries, TSMC’s Kumamoto Fab 1, a joint investment between TSMC, Sony Semiconductor Solutions Corporation, and Denso Corporation, was inaugurated in February. Construction of the second Kumamoto fab is slated to begin by the end of 2024, with operations starting by the end of 2027.

UMC, Taiwan’s second-largest wafer foundry, announced on May 21st the arrival of the first equipment tools for phase 3 expansion at its Fab12i located in Singapore. According to a report by CNA, UMC anticipates the construction of the facility will be completed by mid-year. However, due to adjustments in customer orders, mass production has been delayed by six months to early 2026.

In October, 2023, Powerchip Semiconductor Manufacturing Corporation (PSMC), in collaboration with SBI Holdings, Inc., announced plans regarding its first semiconductor wafer plant in Japan, which is expected to be located in the Second Northern Sendai Central Industrial Park in Ohira Village, Kurokawa District, Miyagi Prefecture (Second Northern Sendai Central Industrial Park).

Previous reports indicated that PSMC plans to construct multiple plants, with the first phase potentially starting construction as early as 2024, involving an investment of around JPY 400 billion (USD 2.6 billion).

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(Photo credit: TSMC)

According to reports from Korean news outlet FN News and Wccftech, aiming to win back NVDIA as a major customer, Samsung has made it a priority to secure chip order from the GPU heavyweight this year. To achieve this, Samsung is reportedly doing everything possible to ensure the company’s 3nm process node, which uses GAA (Gate-All-Around) architecture, meets NVIDIA’s requirements.

Sources quoted by the reports indicated that Samsung has implemented an internal strategy called “Nemo,” specifically targeting NVIDIA. Its foundry now plans to commence mass production of the 3nm GAA process in the first half of 2024. The GAA technology is expected to overcome significant bottlenecks associated with the previous FinFET processes, but it is still uncertain if this will be sufficient to persuade NVIDIA.

NVIDIA has been cooperating with TSMC in advanced process nodes for developing its GPUs for quite a while, both in consumer and data center markets. The tech giant’s latest GPU families, including Ada Lovelace, Hopper, and Blackwell, are all manufactured using TSMC’s 5nm (4N) processes, according to the aforementioned reports.

It’s important to note that NVIDIA last used Samsung’s 8nm process for its GeForce RTX 30 “Ampere” GPUs, designed for the gaming segment. However, the successor to Ampere, the Ada Lovelace “GeForce RTX 40,” switched to TSMC’s 5nm process.

Considering the high demand for NVIDIA’s GPUs, the chipmaker is expected to procure chips from multiple semiconductor fabs, which is simliar to its previous strategy of dual-sourcing HBM and packaging materials, according to Wccftech.

(Photo credit: Samsung)

Intel’s early adoption of ASML’s High Numerical Aperture Extreme Ultraviolet Lithography (High-NA EUV) equipment is seen by many as a crucial move for Intel to reclaim its technological leadership. Yet, according to a report from CNA, industry sources cited in the report have warned that the high cost of High-NA EUV could lead Intel to face the dilemma of expanding losses.

As Intel secures High-NA EUV equipment, the Korean media outlet TheElec reported that ASML plans to manufacture five High-NA EUV equipment this year, all of which have been booked by Intel. TSMC’s decision to continue using existing EUV equipment for its A16 process, rather than adopting High-NA EUV, has drawn significant attention and sparked lively discussion.

Per a report from Reuters, Intel CEO Pat Gelsinger has acknowledged that the previous decision to oppose using ASML’s EUV equipment was a mistake, which hampered the profitability of Intel’s foundry business. He stated that, with the adoption of EUV equipment, Intel is now highly competitive in terms of price and performance. There is widespread interest in whether Intel’s early adoption of High-NA EUV equipment will help it regain its position as a technology leader.

On the other hand, TSMC plans to mass-produce its A16 technology by 2026, combining nanosheet transistors with a supertrack architecture, garnering attention from the industry.

Ray Yang, the consulting director at Industry, Science and Technology International Strategy Center of ITRI (Industrial Technology Research Institute), stated that TSMC’s decision not to adopt High-NA EUV equipment for the A16 process was likely made after a comprehensive evaluation.

Yang mentioned that TSMC is undoubtedly aware of the benefits that High-NA EUV equipment can bring. However, given the high costs, TSMC has chosen to meet its customers’ diverse needs through other means.

According to ASML, High-NA EUV equipment increases the numerical aperture from 0.33 to 0.55, providing higher-resolution imaging capabilities. This improvement enhances precision and clarity, simplifies the manufacturing process, reduces production time, and boosts production efficiency.

During a technical symposium in Amsterdam on May 14th, TSMC’s Senior Vice President of Business Development and Co-Chief Operating Officer, Dr. Kevin Zhang, remarked that ‘I like the high-NA EUV’s capability, but I don’t like the sticker price.’

Each EUV system from ASML costs around USD 180 million, while High-NA EUV equipment is priced at USD 380 million, more than double the cost of EUV.

Ray Yang noted that the importance of advanced semiconductor packaging is increasing and will play a crucial supporting role. He argued that Intel’s rush to acquire High-NA EUV equipment is a case of choosing the wrong battlefield and weapon because High-NA EUV equipment is not the sole decisive factor for future success.

Ray Yang stated that as the global leader in semiconductor foundry services, TSMC has numerous customers, a comprehensive ecosystem, and ample capital. If customers demand and are willing to pay higher prices, TSMC will undoubtedly adopt High-NA EUV equipment.

Yang noted that TSMC is taking a cautious approach to adopting High-NA EUV equipment, likely after thoroughly considering its necessity. If Intel makes significant purchases of High-NA EUV equipment, its future capacity utilization will be worth observing, as it might face the risk of increased losses.

Currently, both TSMC and Samsung utilize EUV equipment for manufacturing, covering TSMC’s 7nm, 5nm, and 3nm processes and Samsung’s EUV Line (7nm, 5nm, and 4nm) located in Hwaseong, Korea, along with the 3nm GAA process.

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(Photo credit: ASML)

The world’s four major CSPs (Cloud Service Providers) – Microsoft, Google, Amazon, and META – are continuously expanding their AI infrastructure, with their combined capital expenditures projected to reach USD 170 billion this year. According to the industry sources cited in a report from Commercial Times, it’s pointed out that due to the surge in demand for AI chips and the increased area of silicon interposers, the number of chips that can be produced from a single 12-inch wafer is decreasing. This situation is expected to cause the CoWoS (Chip on Wafer on Substrate) production capacity under TSMC to remain in short supply.

Regarding CoWoS, according to TrendForce, the introduction of NVIDIA’s B series, including GB200, B100, B200, is expected to consume more CoWoS production capacity. TSMC has also increased its demand for CoWoS production capacity for the entire year of 2024, with estimated monthly capacity approaching 40,000 by the year-end, compared to an increase of over 150% from the total capacity in 2023. A possibility exists for the total production capacity to nearly double in 2025.

However, with NVIDIA releasing the B100 and B200, the interposer area used by a single chip will be larger than before, meaning the number of interposers obtained from a 12-inch wafer will further decrease, resulting in CoWoS production capacity being unable to meet GPU demand. Meanwhile, the number of HBM units installed is also multiplying.

Moreover, in CoWoS, multiple HBMs are placed around the GPU, and HBMs are also considered one of the bottlenecks. Industry sources indicate that HBM is a significant challenge, with the number of EUV (Extreme Ultraviolet Lithography) layers gradually increasing. For example, SK Hynix, which holds the leading market share in HBM, applied a single EUV layer during its 1α production phase. Starting this year, the company is transitioning to 1β, potentially increasing the application of EUV by three to four times.

In addition to the increased technical difficulty, the number of DRAM units within HBM  has also increased with each iteration. The number of DRAMs stacked in HBM2 ranges from 4 to 8, while HBM3/3e increases this to 8 to 12, and HBM4 will further raise the number of stacked DRAMs to 16.

Given these dual bottlenecks, overcoming these challenges in the short term remains difficult. Competitors are also proposing solutions; for instance, Intel is using rectangular glass substrates to replace 12-inch wafer interposers. However, this approach requires significant preparation, time, and research and development investment, and breakthroughs from industry players are still awaited.

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(Photo credit: NVIDIA)