As Apple keeps advancing in AI as well as developing its own in-house processors, industry sources indicated that the tech giant’s Chief Operating Officer (COO) Jeff Williams recently made a visit to TSMC, and was personally received by TSMC’s President, C.C. Wei, according a report by Economic Daily News.

The low-profile visit was made to secure TSMC’s advanced manufacturing capacity, potentially 2nm process, booked for Apple’s in-house AI-chips, according to the report.

Apple has been collaborating with TSMC for many years on the A-series processors used in iPhones. In recent years, Apple initiated the long-term Apple Silicon project, creating the M-series processors for MacBook and iPad, with Williams playing a key role. Thus, his recent visit to Taiwan has garnered significant industry attention.

Apple did not respond to the rumor. TSMC, on the other hand, has maintained its usual stance, not commenting on market speculations related to specific customers.

According to an earlier report from The Wallstreet Journal, Apple has been working closely with TSMC to design and produce its own AI chips tailored for data centers in the primary stage. It is suggested that Apple’s server chips may focus on executing AI models, particularly in AI inference, rather than AI training, where NVIDIA’s chips currently dominate.

Also, in a bid to seize the AI PC market opportunity, Apple’s new iPad Pro launched in early May has featured its in-house M4 chip. In an earlier report by Wccftech, Apple’s M4 chip adopts TSMC’s N3E process, aligning with Apple’s plans for a major performance upgrade for Mac.

In addition to Apple, with the flourishing of AI applications, TSMC has also reportedly beening working closely with the other two major AI giants, NVIDIA and AMD. It’s reported by the Economic Daily News that they have secured TSMC’s advanced packaging capacity for CoWoS and SoIC packaging through this year and the next, bolstering TSMC’s AI-related business orders.

Read more

• [News] Apple M4 Incoming, Boosting TSMC’s 3nm Production
• [News] Apple Unveiled M4 Chip for AI, Heralding a New Era of AI PC

(Photo credit: TSMC)

In addition to the aggressive overseas expansion plans recently, TSMC also demonstrates its ambition of increasing specialty capacity, targeting to be expanded by 50% by 2027, according to a report by AnandTech. A key driver of this demand will be TSMC’s forthcoming specialty node, N4e, a 4nm-class ultra-low-power production node.

Citing Kevin Zhang, TSMC’s Senior Vice President of the Business Development and Overseas Operations Office, the report revealed that TSMC plans to expand its specialty capacity by up to 1.5 times in the next four to five years. To accomplish this goal, it would not only convert existing capacity, but construct new fab space dedicated to specialty processes.

TSMC offers a range of specialty nodes catering to various applications such as power semiconductors, mixed analog I/O, and ultra-low-power applications (e.g., IoT), according to the report. Currently, the semiconductor giant’s most advanced specialty node is N6e, a variant derived from N7/N6 that accommodates operating voltages ranging from 0.4V to 0.9V. With N4e, TSMC aims to support voltages below 0.4V.

According to the materials TSMC provided in its latest earnings call, in the first quarter, HPC accounted for 46% of its total revenue, while IoT-related and automotive applications accounted for 6% of its total revenue, respectively. All the applications mentioned above are closely connected to specialty nodes.

TSMC’s overseas expansion plans are also closely related to its focus on specialty nodes. At the grand opening of JASM’s first Kumamoto plant in February, TSMC Chairman Mark Liu stated that JASM would use the latest green manufacturing practices to produce best-in-class specialty semiconductor technology.

Read more

• [News] TSMC Reportedly Prepares Next-generation HBM4 Manufacturing, Utilizing 12nm and 5nm Process Nodes

(Photo credit: TSMC)

Paul de Bot, President of TSMC Europe, confirmed during a seminar in the Netherlands on May 14th that TSMC will start construction of its first chip plant in Europe in Dresden, eastern Germany. The project is scheduled to commence in the fourth quarter of this year, with production expected to begin in 2027.

Last August, TSMC announced the joint venture factory project in Germany, with a total investment of USD 11 billion. Apart from TSMC, Infineon, NXP, and Bosch each holds a 10% stake.

According to a report from Reuters, Kevin Zhang, Senior Vice President of Business Development and Overseas Operations Office at TSMC, stated that the project has received strong support from the European Union and the German government, thus TSMC is confident in obtaining subsidies under the European Chips Act.

Kevin Zhang stated that the semiconductor ecosystem in Europe is currently exciting, indicating that setting up a foundry in Germany would allow TSMC to directly access its major automotive customers.

It is understood that TSMC’s fab in Germany will initially focus on the 22-nanometer process, mainly producing automotive microcontrollers. There is a possibility of expanding to produce more advanced chips in the future.

In addition, Intel, another semiconductor giant, had also planned a significant investment of EUR 30 billion for constructing two new fabs in Magdeburg, Eastern Germany.

TSMC’s global expansion has reached locations in China, the United States, Japan, and Germany, solidifying its goal of being a “long-term and trustworthy provider of technology and capacity.”

TSMC’s Kumamoto Plant in Japan held its opening ceremony in February, with mass production expected to begin in the fourth quarter. Kevin Zhang also emphasized that TSMC will continue to expand its operations in Japan.

In response to growing customer demand, TSMC announced in February plans to begin construction of its Kumamoto Fab 2 by the end of the year, which will be its second, more advanced fab in Japan, scheduled to start operations by the end of 2027.

In contrast, the construction progress of its Arizona plant in the United States has been relatively slow. Due to the delay in the first phase’s production timeline from the end of 2024 to the first half of 2025, the production schedule for the second phase will also be postponed to start after 2027.

Read more

• [News] Latest Overview on TSMC’s Global Expansion Initiatives
• [News] Kumamoto Vying for TSMC’s Third Fab, Looking to Build Semiconductor Hub

According to a report from global media outlet Wccftech, China’s largest foundry, SMIC, is rumored to produce 5-nanometer chips for Huawei this year, without the need for extreme ultraviolet (EUV) lithography machines manufactured by Dutch company ASML.

As per a report by Businesskorea, SMIC seems to be able to use old deep ultraviolet (DUV) lithography machines purchased before the sanctions were implemented to manufacture 5-nanometer chips. However, this would incur higher costs and could also affect yields.

Previously reported by the Financial Times, industry sources have indicated that SMIC’s prices for 5-nanometer and 7-nanometer processes are 40% to 50% higher than TSMC’s, and the yield less than one-third of TSMC’s. Later, it was estimated that SMIC’s 5nm chip prices would be up to 50 percent more expensive than TSMC’s on the same lithography, meaning that Huawei would face a tough time selling its Mate 70 series to consumers with a decent margin if it attempts to absorb a majority of those component costs.

Huawei was previously said to be working closely with its local foundry partner to introduce a new Kirin SoC that will be found in the upcoming Mate 70 series, scheduled to be released in October, with SMIC’s 5nm process has been said completed and is ready to mass produce the first batch of wafer.

This means that if Huawei attempts to absorb most of these costs, it will face the challenge of insufficient profit margins when selling the Mate 70 series to consumers. The tech giant may attract customers by promoting its in-house HarmonyOS Next, which is reportedly set to debut with the Mate 70 series. The model is said to be equipped with better efficiency in memory management compared to Google’s Android platform, according to Wccftech.

Meanwhile, Intel has recently secured its supply of the new High-NA EUV (high-numerical aperture extreme ultraviolet) lithography equipment from ASML, which the semiconductor heavyweight will allegedly use on its 18A (1.8nm) and 14A (1.4nm) nodes, according to a report from TheElec.

On the other hand, according to sources cited by a report from Economic Daily News, TSMC’s A16 advanced process node might not necessarily require ASML’s latest advanced chip manufacturing equipment, the High Numerical Aperture Extreme Ultraviolet Lithography (High-NA EUV), due to its expensive price.

Read more

• [News] How Costly is the High-NA EUV? TSMC Reportedly Shocked, Considering Not Using the Equipment in its A16 Node
• [News] Intel Secures First Batch of High-NA EUV Equipment from ASML, Ahead of Samsung and SK Hynix

(Photo credit: SMIC)

According to sources cited by a report from Economic Daily News, TSMC’s A16 advanced process node might not necessarily require ASML’s latest advanced chip manufacturing equipment, the High Numerical Aperture Extreme Ultraviolet Lithography (High-NA EUV), due to its expensive price.

Per a report from Bloomberg, during a technical symposium in Amsterdam on May 14th, TSMC’s Senior Vice President of Business Development and Co-Chief Operating Officer, Dr. Kevin Zhang, remarked that while he appreciates the capabilities of High-NA EUV, he finds its price tag to be unlikeable.

As per the same report from Bloomberg, ASML’s new machine is capable of imprinting semiconductors with lines measuring just 8 nanometers in thickness — 1.7 times smaller than the previous generation.

In terms of pricing, this EUV machine is reportedly priced at EUR 350 million (roughly USD 380 million), with a weight equivalent to two Airbus A320 passenger planes, according to Bloomberg.

Dr. Kevin Zhang stated that TSMC’s planned A16 node (scheduled for volume production slightly later in 2026) may not necessarily require the use of ASML’s High NA EUV equipment. Instead, TSMC could continue to rely on its existing, older EUV equipment. “I think at this point, our existing EUV capability should be able to support that,” he expressed.

He further mentioned that the decision to adopt the new ASML technology would depend on where it offers the most economic benefits and the technical balance they can achieve. He declined to disclose when TSMC might purchase High-NA EUV from ASML.

On the other hand, Intel has confirmed in mid-April that it has received and assembled the industry’s first High-NA EUV lithography system, which is expected to be able to print features up to 1.7x smaller than existing EUV tools. This will enable 2D feature scaling, resulting in up to 2.9x more density.

Currently, both TSMC and Samsung utilize EUV equipment for manufacturing, covering TSMC’s 7nm, 5nm, and 3nm processes and Samsung’s EUV Line (7nm, 5nm, and 4nm) located in Hwaseong, Korea, along with the 3nm GAA process.

Read more

• [News] Intel Secures First Batch of High-NA EUV Equipment from ASML, Ahead of Samsung and SK Hynix
• [News] EUV as a Strategic Asset in the Most Advanced Processes: Progress in Intel/TSMC/Samsung’s Adoptions

(Photo credit: ASML)