According to a report from Korean media The Korea Economic Daily, Samsung Electronics Co. is planning to apply its 3nm process chips to its Galaxy series smartphones and smartwatches, posing a challenge to rivals Apple and TSMC.

The report cited industry sources on May 13th, stating that Samsung’s second-generation 3nm production line in South Korea is set to commence operations in the latter half of this year (2024). The first product to be manufactured on this line will reportedly be the application processor (AP) for the upcoming Galaxy Watch7, tentatively named “Exynos W1000,” which is expected to be unveiled in July.

As per the same report citing sources, the Exynos W1000 is set to utilize the semiconductor industry’s most advanced second-generation 3nm process, with computing performance and power efficiency expected to increase by over 20%. In comparison, the Apple Watch Series 9 utilizes a 5nm application processor.

On another note, industry sources cited by the same report revealed that Samsung’s next-generation flagship smartphone, the Galaxy S25, scheduled for an early 2025 release, will also feature the 3nm Exynos W1000 application processor. Samsung aims to unveil this technology ahead of the Paris Summer Olympics opening on July 26th, with a “Galaxy Unpacked” event scheduled for July 10th in Paris.

The mobile processor industry has entered the 3nm battleground. Per Wccftech’s previous report, it is rumored that TSMC’s N3E process is also used for producing products like the A18 Pro chip scheduled to be used in iPhone 16 Pro, the upcoming Qualcomm Snapdragon 8 Gen 4, and the MediaTek Dimensity 9400, among other major clients’ products.

Meanwhile, as per a report from another South Korean media outlet TheElec, Siyoung Choi, the President of Samsung’s Foundry Business, predicted during the annual shareholders’ meeting on March 20th that the second-generation 3nm process is expected to begin production in the latter half of this year, while production for the 2nm process is slated for next year.

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(Photo credit: Samsung)

Taiwan Semiconductor Manufacturing Company (TSMC) has planned to build two fabs in Kumamoto Prefecture, Japan. Kumamoto’s newly appointed governor, Takashi Kimura, who took office in April, stated in an report from Bloomberg on May 11th that he would spare no effort to persuade TSMC to establish a third fab in the region. He has already proposed a visit to TSMC’s headquarters in Taiwan this summer to discuss related matters, aiming to transform Kumamoto into a semiconductor hub.

TSMC has not responded to this matter. While TSMC’s third fab in Kumamoto, as mentioned by Governor Kimura, has not materialized yet, and TSMC has not officially announced it, Bloomberg previously reported that TSMC is considering building a third fab in Japan, which would also be located in Kumamoto and produce more advanced chips.

Regarding the rumored TSMC Kumamoto Fab 3, Takashi Kimura stated, “We are prepared to give our full support.” He expressed his hope to attract numerous semiconductor-related enterprises and research institutions to Kumamoto, aiming to establish an industrial cluster similar to Taiwan’s Hsinchu Science Park. He also hopes Kumamoto will become a birthplace for various industries stemming from semiconductors, including AI, data centers, and autonomous driving technologies.

Kimura believes that during the preparations for TSMC’s first fab in Kumamoto, the region already possesses better-quality road and water infrastructure and an education system that better supports international school students, which could be advantageous.

TSMC’s Kumamoto Fab 1, a joint investment between TSMC, Sony Semiconductor Solutions Corporation, and Denso Corporation, was inaugurated in February. TSMC stated in an earlier press release that in response to customer demand, construction of the second JASM (TSMC’s majority-owned manufacturing subsidiary in Kumamoto Prefecture) fab is slated to begin by the end of 2024. The expansion of production capacity is also expected to optimize the overall cost structure and supply chain efficiency of JASM, with operations starting by the end of 2027.

In the future, the two fabs under JASM will enable a total monthly production capacity of over 100,000 12-inch wafers, providing 40-nanometer, 22/28-nanometer, 12/16-nanometer, and 6/7-nanometer processes for automotive, industrial, consumer, and high-performance computing (HPC) applications.

Capacity planning may be adjusted according to customer demand, with the Kumamoto fab directly creating a total of over 3,400 high-tech job opportunities. Through the investment, TSMC, Sony Semiconductor, Denso Corporation, and Toyota Motor Corporation hold approximately 86.5%, 6.0%, 5.5%, and 2.0% of the JASM shares, respectively.

The Kyushu Economic Research Association estimates that these fabs will contribute JPY 10.5 trillion (USD 67.4 billion) to the economy of Kumamoto Prefecture over the next decade.

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(Photo credit: TSMC)

As Moore’s Law progresses, transistors are becoming smaller and denser, with more layers stacked on top of each other. This may require passing through 10 to 20 layers of stacking to provide power and data signals to the transistors below, leading to increasingly complex networks of interconnects and power lines. Simultaneously, as electrons transmit downward, IR drop phenomena occur, resulting in power loss.

Apart from power loss, the occupation of space by power supply lines is also a concern, which often occupies at least 20% of resources. Addressing the issue of signal network and power supply network resource contention to miniaturize components becomes a major challenge for chip designers. As per a report from TechNews, this has led the semiconductor industry to begin shifting power supply networks to the backside of chips.

• TSMC’s Super Rail Technology Set to Revolutionize Chip Efficiency with A16 Process Node Debut in 2025

Leading semiconductor foundry TSMC recently unveiled its A16 process at a technical forum in North America.

This new node not only accommodates more transistors, enhancing computational efficiency, but also reduces energy consumption. Of particular interest is the integration of the Super PowerRail architecture and nanosheet transistors in the A16 chip, driving the development of data center processors that are faster and more efficient.

Notably, TSMC’s A16 employs a different chip wiring manner, with power wires delivering electricity to transistors located beneath rather than above them, known as backside power supply, facilitating the production of more efficient chips.

In fact, one of the methods to optimize processors is to alleviate IR drop, a phenomenon that reduces the voltage received by the transistors on the chip, consequently affecting performance. The A16 wiring is less prone to voltage drops, simplifying power distribution and allowing for tighter chip packaging, aiming to accommodate more transistors to enhance computational capabilities.

Additionally, TSMC’s A16 process technology directly connects the power transmission lines to the source and drain of the transistor, which improves chip efficiency.

Using the Super PowerRail in A16, TSMC achieves an 10% higher clock speed or a 15% to 20% decrease in power consumption at the same operating voltage (Vdd) compared to N2P. Moreover, the chip density is increased by up to 1.10 times, supporting data center products.

• Intel’s PowerVia Set for Production on Intel 20A in 2024

Similar to TSMC’s Super PowerRail, Intel has also introduced its backside power delivery solution, PowerVia.

According to Intel, power lines typically occupy around 20% of the space on the chip surface, but PowerVia’s backside power delivery technology saves this space, allowing  more flexibility in the interconnect layers.

In addition, the Intel team previously created the Blue Sky Creek test chip to demonstrate the benefits of backside power delivery technology. Test results indicated that most areas of the chip achieved over 90% cell utilization, with a 30% platform voltage droop improvement, 6% frequency benefit, increased unit density, and potential cost reduction. The PowerVia test chip also exhibited excellent heat dissipation properties, aligning with expectations for higher power density as logic shrinks.

Furthermore, PowerVia is slated to be integrated into Intel Foundry Services (IFS), enabling faster achievement of product efficiency and performance enhancements for customer-designed chips.

According to official documentation from Intel, the tech giant plans to implement PowerVia on Intel 20A process technology along with the RibbonFET architecture for the full-surround gate transistor. Production readiness is expected in the first half of 2024, with initial steps being taken at the fabrication plant for future mass production of client ARL platforms.

• Samsung Plans to Implement SF1.4 Process by 2027

In addition to leading the transition to GAA transistor technology, Samsung, another competitor of TSMC, is also wielding its Backside Power Delivery Network as a key weapon in the pursuit of advanced processes.

According to a previous report from Samsung, Jung Ki-tae Jung, Chief Technology Officer of Samsung’s foundry division, announced plans to apply the backside power delivery technology to the 1.4-nanometer process by 2027.

Reports from Korean media outlet theelec indicate that compared to traditional front-end power delivery networks, Samsung’s backside power delivery network successfully reduces wafer area consumption by 14.8%, providing more space on the chip to accommodate additional transistors, thereby enhancing overall performance.

Additionally, wiring length is reduced by 9.2%, aiding in resistance reduction to allow more current flow, leading to lower power consumption and improved power transmission conditions. Samsung Electronics representatives noted that the mass production timeline for semiconductor chips adopting backside power delivery technology may vary depending on customer schedules, and Samsung is currently investigating customer demand for the application of this technology.

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With the skyrocketing demand for AI, cloud service providers (CSPs) are hastening the development of in-house chips. Apple, making a surprising move, is actively developing a data center-grade chip codenamed “Project ACDC,” signaling its foray into the realm of AI accelerators for servers.

As per a report from global media The Wall Street Journal, Apple is developing an AI accelerator chip for data center servers under the project name “Project ACDC.” Sources familiar with the matter revealed that Apple is closely collaborating with TSMC, but the timing of the new chip’s release remains uncertain.

Industry sources cited by the same report from Commercial Times disclosed that Apple’s AI accelerator chip will be developed using TSMC’s 3-nanometer process. Servers equipped with this chip are expected to debut next year, further enhancing the performance of its data centers and future cloud-based AI tools.

Industry sources cited in Commercial Times‘ report reveal that cloud service providers (CSPs) frequently choose TSMC’s 5 and 7-nanometer processes for their in-house chip development, capitalizing on TSMC’s mature advanced processes to enhance profit margins. Additionally, the same report also highlights that major industry players including Microsoft, AWS, Google, Meta, and Apple rely on TSMC’s advanced processes and packaging, which significantly contributes to the company’s performance.

Apple has consistently been an early adopter of TSMC’s most advanced processes, relying on their stability and technological leadership. Apple’s adoption of the 3-nanometer process and CoWoS advanced packaging next year is deemed the most reasonable solution, which will also help boost TSMC’s 3-nanometer production capacity utilization.

Generative AI models are rapidly evolving, enabling businesses and developers to address complex problems and discover new opportunities. However, large-scale models with billions or even trillions of parameters pose more stringent requirements for training, tuning, and inference.

Per Commercial Times citing industry sources, it has noted that Apple’s entry into the in-house chip arena comes as no surprise, given that giants like Google and Microsoft have long been deploying in-house chips and have successively launched iterative products.

In April, Google unveiled its next-generation AI accelerator, TPU v5p, aimed at accelerating cloud-based tasks and enhancing the efficiency of online services such as search, YouTube, Gmail, Google Maps, and Google Play Store. It also aims to improve execution efficiency by integrating cloud computing with Android devices, thereby enhancing user experience.

At the end of last year, AWS introduced two in-house chips, Graviton4 and Trainium2, to strengthen energy efficiency and computational performance to meet various innovative applications of generative AI.

Microsoft also introduced the Maia chip, designed for processing OpenAI models, Bing, GitHub Copilot, ChatGPT, and other AI services.

Meta, on the other hand, completed its second-generation in-house chip, MTIA, designed for tasks related to AI recommendation systems, such as content ranking and recommendations on Facebook and Instagram.

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(Photo credit: Apple)

According to a report from Economic Daily News citing The Wallstreet Journal, Apple is rumored to be developing its own AI chips tailored for data centers, which could potentially give the world’s top smartphone seller a crucial advantage in the AI arms race. The report, quoting sources familiar with the matter, stated that Apple has been working closely with its chip manufacturing partner TSMC to design and produce these chips in the primary stage. However, it is still unclear whether the final version has been produced yet.

It is suggested that Apple’s server chips may focus on executing AI models, particularly in AI inference, rather than AI training, where Nvidia’s chips currently dominate.

Over the past decade, Apple has gradually become a major player in chip design for products like iPhone, iPad, Apple Watch, and Mac. The latest project involving Apple chips for data center servers, internally named “Project ACDC” (short for Apple Chips in Data Center), will integrate Apple’s IC design capabilities into the operation of clients’ servers, sources said.

The project has been in operation for several years, though the timetable for launching this server chip remains unclear. Apple is expected to unveil more new AI products and AI-related updates at its Worldwide Developers Conference (WWDC) in June.

An Apple spokesperson declined to comment on the reported developments.

According to reports from Wccftech on April 23rd, Apple is said to be working on a self-developed AI server processor using TSMC’s 3-nanometer process, with plans for mass production expected in the second half of 2025.