Following TSMC’s announcement of investing USD 20 billion to build two plants in Kumamoto, Japan, industry sources cited by a report from Commercial Times has indicated that the major global semiconductor assembly and testing provider, ASE Group, is in discussions with the Japanese government to finalize subsidies and investment details.

Reportedly, ASE plans to invest nearly NTD 10 billion (roughly USD 306.3 million) to construct its first advanced packaging plant in Kumamoto, becoming the second Taiwanese semiconductor giant to set foot in the region.

Regarding the establishment of a plant in Kumamoto, ASE Group stated that it does not comment on market rumors.

During its earnings call last week, ASE Group announced a capital expenditure increase to expand related capacities due to the upward adjustment in advanced packaging projects. This year’s capital expenditure, originally estimated at around USD 2.1 billion with a year-on-year increase of over 40%, has been raised to a potential 50% increase (up to USD 2.25 billion), potentially reaching a historic high.

The semiconductor industry is witnessing a great era of global competition with various countries pouring money into subsidies. Recently, there have been rumors of the Japanese government actively reaching out to Taiwanese semiconductor companies and offering substantial subsidies, aiming to build a complete semiconductor industry chain covering upstream, midstream, and downstream sectors.

Apart from TSMC’s decision to establish two advanced semiconductor plants in Kumamoto, Intel is also considering establishing an advanced packaging research institution in Japan, and Samsung is planning to set up advanced packaging research facilities in Yokohama.

Industry sources cited by the same report point out that these signs have indicated that after mastering wafer manufacturing technology, the next phase for Japan is to enhance the establishment of the packaging industry.

Industry rumors have recently circulated that the Japanese government has been in discussions with senior executives from ASE Group for some time, and the relevant subsidy and investment details are generally agreed upon. The location for the new facility is expected to be in Kumamoto, near TSMC’s upcoming plant. As per the same report citing sources, there is a chance that ASE’s Kumamoto facility, like TSMC’s second plant in Kumamoto, will be planned to start production before the end of 2027.

In fact, as early as 2004, ASE Group acquired full ownership of an IC packaging and testing facility in Yamagata Prefecture, Japan, from NEC for USD 80 million. However, over the past two decades, Japan’s influence in the global semiconductor sector has waned, and ASE’s acquisition of the NEC facility has not made significant operational contributions.

ASE Group’s global footprint currently includes high-end product bases in Taiwan, as well as its packaging and testing capacities in China, Japan, Malaysia, South Korea, and Singapore.

ASE is continuing its expansion efforts in Taiwan, including Kaohsiung, Zhongli, and Tanzi. Evenmore, on February 22nd, ASE Group and semiconductor giant Infineon Technologies jointly announced the finalization of an agreement. ASE Group will invest EUR 62.589 million to acquire Infineon’s backend packaging facilities located in Cavite, Philippines, and Cheonan, South Korea.

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TSMC unveiled its angstrom-class A16 advanced process during the Company’s 2024 North America Technology Symposium on April 25, set to be mass-produced in 2026. Not only is this earlier than competitors like Intel’s 14A and Samsung’s SF14, both slated for 2027 production, but TSMC also emphasized that the A16 does not require the use of High-NA EUV, making it more cost-competitive.

TSMC’s A16 to Lead Competitors in Production Time and Cost

According to TSMC, the A16 advanced process, combining Super PowerRail and nanosheet transistors, is set for mass production in 2026. Super PowerRail relocates power networks to the backside of wafers, freeing up more space on the frontside for signal networks, enhancing logic density and performance. This is ideal for High-Performance Computing (HPC) products with complex signal routing and dense power networks.

Compared to TSMC’s N2P process, the A16 offers an 8% to 10% speed increase at the same Vdd (operating voltage), a 15% to 20% reduction in power consumption at the same speed, and a density increase of up to 1.1 times, supporting data center products.

Photo credit: TSMC

Additionally, as AI chip companies are eager to optimize designs to leverage the full potential of TSMC’s processes, as per a report from Reuters, TSMC doesn’t believe that ASML’s latest High-NA EUV is necessary for producing A16 process chips.

Furthermore, TSMC showcased the Super Power Rail architecture, slated to be operational in 2026, which delivers power from the backside of the chip, aiding in the accelerated operation of AI chips.

Intel 14A Extends ‘5 Nodes in 4 Years’ Strategy

In February, Intel unveiled its 14A process, which would be after its “5 Nodes in 4 Years” strategy. After integrating High-NA EUV production, Intel 14A is expected to improve energy efficiency by 15% and increase transistor density by 20% compared to Intel 18A.

The enhanced version, Intel 14A-E, will further boost energy efficiency by 5% based on Intel 14A. According to the plan, Intel 14A is set for mass production as early as 2026, while Intel 14A-E is slated for 2027.

Photo credit: Intel

Intel recently announced the completion of the industry’s first commercial High-NA EUV lithography tool assembly. The ASML TWINSCAN EXE:5000 High-NA EUV lithography tool is undergoing multiple calibrations and is scheduled to be operational in 2027 for Intel’s 14A process.

Intel emphasizes that when the High-NA EUV lithography tool is combined with its other leading process technologies, it reduces print size by 1.7 times compared to existing EUV machines. This reduction in 2D dimensions increases density by 2.9 times, aiding Intel in advancing its process roadmap.

Samsung SF1.4 Enhances Performance and Power Efficiency with Nanosheet Addition

Photo credit: Samsung

Compared to TSMC and Intel, Samsung’s progress in the angstrom era seems somewhat lagging. Two years ago at the Samsung Foundry Forum 2022, Samsung unveiled its advanced process roadmap, with the angstrom-level SF1.4 (1.4 nanometers) set for mass production in 2027.

Last October, Samsung’s Vice President of Foundry, Jeong Gi-Tae, reportedly told the Korean media outlet The Elec that Samsung has announced its upcoming SF1.4 (1.4-nanometer class) process technology, which would increase the number of nanosheets from 3 to 4. This move is expected to bring significant benefits in chip performance and power consumption

Samsung announced the mass production of SF3E (3nm GAA) in June 2022, introducing a new Gate-All-Around (GAA) architecture. This year, they unveiled the second-generation 3nm process, SF3 (3nm GAP), utilizing the second-generation Multi-Bridge Channel Field Effect Transistor (MBCFET) to optimize performance based on the SF3E foundation.

Additionally, they introduced the performance-enhanced SF3P (3GAP+), suitable for manufacturing high-performance chips. By 2025, Samsung plans to scale up production of the SF2 (2nm) process, followed by mass production of the SF1.4 (1.4nm) process in 2027.

Reportedly, Samsung aims to increase the number of nanosheets per transistor to enhance drive current and improve performance. More nanosheets allow higher current to pass through the transistor, enhancing switching capability and operational speed.

Moreover, more nanosheets offer better control over current, helping to reduce leakage and lower power consumption. Improving current control means transistors generate less heat.

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Henri Richard, head of Rapidus Design Solutions, the US subsidiary of Japan’s semiconductor foundry startup Rapidus, and former Chief Marketing Officer at processor giant AMD, indicates that Rapidus aims to position itself as a filler of market gaps during the interview with global media The Register.

Rapidus Design Solutions, established by Rapidus in this month, is expected to bolster ties with US semiconductor design companies and wafer manufacturing technology providers like IBM. Henri Richard reportedly notes that the AI boom is boosting the advanced semiconductor foundry market, albeit with understated demand and ongoing capacity constraints. Thus, in this market trend, he asserts that even if these technologies don’t necessarily confer a competitive edge, the limitations in capacity alone should suffice to ensure Rapidus’ success.

Established in August 2022, Rapidus was jointly founded by eight Japanese companies, including Toyota, Sony, NTT, NEC, Softbank, Denso, Kioxia (formerly Toshiba Memory Corporation), and Mitsubishi UFJ, who invested collectively in its establishment. As per Rapidus’ plan, they aim to commence mass production of 2-nanometer process technology in 2027, significantly lagging behind major global players like TSMC, Intel, and Samsung.

TSMC and Samsung previously planned to mass-produce 2nm chips in 2025, while Intel is anticipated to be the first to achieve commercialization of 2nm chips. Industry sources cited by the The Register’s report also view this timing as unfavorable for Rapidus.

However, Henri Richard believes that the semiconductor process technology has reached a turning point. Assessing the success of suppliers solely based on production timelines is narrow-minded; competitiveness stems from various factors beyond production schedules.

Based on these factors, Rapidus positions itself as a fill-in player in the advanced manufacturing market, targeting small AI chip design companies as its primary market. While competitors focus on serving large clients, Rapidus aims to win over these smaller clients by offering comprehensive support services. By serving numerous small chip design companies, Rapidus can better understand the specific needs of AI chip users, rather than insisting on the latest process technology for all chips.

Henri Richard emphasizes that Rapidus itself has limited scale and cannot initially serve too many clients simultaneously. It is expected that Rapidus’s initial client base will not exceed 6 companies, allowing them to accumulate experience and capabilities.

Although there are geopolitical issues currently, establishing facilities in the US is not on Rapidus’s immediate agenda. Meanwhile, Japan represents a relatively favorable geographic location for Rapidus, offering clients a risk-diversification option.

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(Photo credit: Rapidus)

TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company’s 2024 North America Technology Symposium.

TSMC debuted the TSMC A16TM technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW™) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

“We are entering an AI-empowered world, where artificial intelligence not only runs in data centers, but PCs, mobile devices, automobiles, and even the Internet of Things,” said TSMC CEO Dr. C.C. Wei. “At TSMC, we are offering our customers the most comprehensive set of technologies to realize their visions for AI, from the world’s most advanced silicon, to the broadest portfolio of advanced packaging and 3D IC platforms, to specialty technologies that integrate the digital world with the real world.”

New technologies introduced at the symposium include:

TSMC A16TM Technology: With TSMC’s industry-leading N3E technology now in production, and N2 on track for production in the second half of 2025, TSMC debuted A16, the next technology on its roadmap.

A16 will combine TSMC’s Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks.

Compared to TSMC’s N2P process, A16 will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15- 20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products.

TSMC NanoFlexTM Innovation for Nanosheet Transistors: TSMC’s upcoming N2 technology will come with TSMC NanoFlex, the company’s next breakthrough in design-technology co optimization. TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Customers are able to optimize the combination of short and tall cells within the same design block, tuning their designs to reach the optimal power, performance, and area tradeoffs for their application.

N4C Technology: Bringing TSMC’s advanced techynology to a broader range of of applications, TSMC announced N4C, an extension of N4P technology with up to 8.5% die cost reduction and low adoption effort, scheduled for volume production in 2025.

N4C offers area-efficient foundation IP and design rules that are fully compatible with the widely-adopted N4P, with better yield from die size reduction, providing a cost-effective option for value-tier products to migrate to the next advanced technology node from TSMC.

CoWoS, SoIC, and System-on-Wafer (SoW): TSMC’s Chip on Wafer on Substrate (CoWoS) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and high-bandwidth memory (HBM) stacks side by side on one interposer. At the same time, our System on Integrated Chips (SoIC) has established itself as the leading solution for 3D chip stacking, and customers are increasingly pairing CoWoS with SoIC and other components for the ultimate system-in-package (SiP) integration.

With System-on-Wafer, TSMC is providing a revolutionary new option to enable a large array of dies on a 300mm wafer, offering more compute power while occupying far less data center space and boosting performance per watt by orders of magnitude.

TSMC’s first SoW offering, a logic only wafer based on Integrated Fan-Out (InFO) technology, is already in production. A chip-on-wafer version leveraging CoWoS technology is scheduled to be ready in 2027, enabling integration of SoIC, HBM and other components to create a powerful wafer-level system with computing power comparable to a data center server rack, or even an entire server.

Silicon Photonics Integration: TSMC is developing Compact Universal Photonic Engine (COUPE ) technology to support the explosive growth in data transmission that comes with the AI boom. COUPE uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods.

TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as co-packaged optics (CPO) in 2026, bringing optical connections directly into the package.

Automotive Advanced Packaging: After introducing the N3AE “Auto Early” process in 2023, TSMC continues to serve our automotive customers’ needs for greater computing power that meets the safety and quality demands of the highway by integrating advanced silicon with advanced packaging.

TSMC is developing InFO-oS and CoWoS-R solutions for applications such as advanced driver assistance systems (ADAS), vehicle control, and vehicle central computers, targeting AEC-Q100 Grade 2 qualification by fourth quarter of 2025.

(Photo credit: TSMC)

According to reports from global media outlets like MacRumors and Wccftech on April 23rd, Apple is said to be developing its first in-house AI processor for PCs, the M4 chip, and is also working on a self-developed AI server processor using TSMC’s 3-nanometer process, with plans for mass production expected in the second half of 2025.

As per Wccftech’s report, based on the production schedule, Apple’s AI server processor might utilize TSMC’s “N3E” process. It is rumored that the N3E process is also used for producing products like the A18 Pro, the upcoming Qualcomm Snapdragon 8 Gen 4, and the MediaTek Dimensity 9400, among other major clients’ products.

Regarding this matter, per a report from Economic Daily News citing sources, it has indicated that Apple’s development of AI server processors will bring new momentum to TSMC’s advanced process orders. Subsequently, assembly orders for related AI servers are expected to be undertaken by Foxconn, becoming two major benefactors of Apple’s aggressive push into AI among Taiwan’s manufacturers.

The source referenced previous reports suggesting that Apple has secured the initial capacity for TSMC’s 3-nanometer process for at least a year. According to TSMC’s financial reports, the revenue contribution from its largest customer exceeded NTD 500 billion in 2022 and is projected to reach NTD 546.5 billion in 2023, setting a new record. TSMC’s largest customer is, anticipated by the report from Economic Daily News, to be Apple.

The same report from Economic Daily News continues by quoting industry sources who revealed that Apple has conducted extensive AI functionality testing, which is highly confidential. Apple and Foxconn have reportedly been engaged in many projects and ongoing tests.

With Apple’s full-scale push into the AI field and plans to introduce AI features in this year’s new iPhone models, there are also rumors of Apple possibly launching its own developed AI chip.

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(Photo credit: Apple)