According to a report by Nikkei News, Japan’s official support for the semiconductor industry expenditure, relative to its gross domestic product (GDP), is significantly higher than that of the United States and other major Western countries.

Figures submitted by a subcommittee under Japan’s Ministry of Finance’s Fiscal System Council show that Japan will invest JPY 3.9 trillion (approximately USD 25.7 billion) over the next three years, equivalent to 0.71% of its GDP. In comparison, the United States will invest more, with JPY 7.1 trillion over five years, but this represents only 0.21% of its GDP, less than one-third of Japan’s ratio.

Over the next five years, France’s expenditure amounts to JPY 700 billion, equivalent to 0.2% of its GDP. Germany’s expenditure stands at JPY 2.5 trillion, equivalent to 0.41% of its GDP.

On Monday, the U.S. Department of Commerce announced a direct subsidy of up to USD 6.6 billion to TSMC, aiming to attract more investments from TSMC within the United States. Meanwhile, in Japan, TSMC secured approximately JPY 1.2 trillion (USD 7.5 billion).

Nikkei notes that Japan’s JPY 3.9 trillion investment in the semiconductor industry involves supplementary budgets, leading to a sharp increase in spending. Thus, the Ministry of Finance is concerned about the lack of funding sources for official support of semiconductor manufacturing. According to Nikkei News, only over JPY 500 billion of Japan’s semiconductor industry expenditures have been covered by actual funds.

One funding source is GX bonds, which the government has started issuing for economic green transformation to achieve net-zero emissions by 2050. GX bonds are expected to raise approximately JPY 20 trillion over the next decade, to be repaid using carbon tax revenue.

TrendForce has previously reported that Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

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• [News] TSMC Receives USD 6.6 Billion for Chipmaking from the US Government, Commits to Constructing Third Fab
• [News] Subsidies to TSMC from Japan and China Increase Over Fivefold Annually

(Photo credit: TSMC)

Amid NVIDIA’s leadership in the AI wave, demand for CoWoS (Chip-on-Wafer-on-Substrate) has tripled, driving TSMC to aggressively expand CoWoS capacity, with a corresponding surge in demand for System-in-Integrated-Circuit (SoIC) solutions.

According to a report from MoneyDJ citing industry sources, it has suggested that in addition to AMD, which has already implemented SoIC in production, Apple is conducting limited trial production. Furthermore, collaborations are underway with NVIDIA and Broadcom, indicating that SoIC is poised to become TSMC’s next advanced packaging solution following CoWoS.

TSMC’s SoIC is the industry’s first high-density 3D chip stacking technology, enabling heterogeneous integration of chips with different sizes, functionalities, and nodes using Chip on Wafer packaging. Currently, production takes place at the AP6 assembly and testing facility in Zhunan, Taiwan. It’s rumored that the planned advanced packaging facility in Chiayi, Taiwan will include not only two CoWoS plants but also an SoIC facility.

AMD is the first customer to adopt SoIC technology, with its latest MI300 chip using SoIC combined with CoWoS solution. Apple, TSMC’s primary customer, is reportedly interested in SoIC and plans to incorporate it with Hybrid molding technology for Mac products. Small-scale trials are currently underway, with mass production anticipated between 2025 and 2026. NVIDIA and Broadcom are also collaborating in this field.

As per the same report citing industry sources, the SoIC technology is still in its early stages, with monthly production capacity expected to reach around 2,000 wafers by the end of this year. There are prospects for this capacity to double this year and potentially exceed 10,000 wafers by 2027.

With support from major players like AMD, Apple, and NVIDIA, TSMC’s expansion in SoIC is viewed as confident, securing future orders for high-end chip manufacturing and advanced packaging.

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• [News] TSMC Reportedly Sensing Increased Orders Again, CoWoS Production Capacity Surges
• [News] TSMC’s SoIC Demand Heats Up, Reports Suggest Significant Capacity Expansion

(Photo credit: TSMC)

As the U.S. Department of Commerce finalizes subsidies for Intel and TSMC, the two major semiconductor manufacturers will enter a new competitive landscape in the United States.

In preparation for these new challenges and with the first fab trial production imminent, sources cited by a report from Liberty Times has revealed that TSMC will dispatch Vice President of Manufacturing Operations, Arthur Chuang, to oversee the Arizona site in May. He will collaborate with TSMC’s vice president of fab operations Dr. Y.L. Wang, signaling TSMC’s accelerated efforts to establish and produce at U.S. fabs concurrently, aiming to achieve a competitive advantage in advanced manufacturing processes in the United States.

Arizona Fab to Begin Trial Production of 4,000 Wafers by Month’s End

Following the confirmation of subsidies for Intel and TSMC by the U.S. Department of Commerce, subsidies for Samsung are also rumored to be announced soon. Industry sources cited in the report from Liberty Times believe that the United States, through these subsidies promoting domestic chip manufacturing and with major clients gathering, will become the primary battlefield for investment in advanced manufacturing processes.

However, with high production costs and the need to rebuild supply chains, TSMC has adjusted its strategy following a series of setbacks at its first fab. After more than a year of installation work, the fab is nearing completion and preparing to embark on a new phase with trial production of approximately 4,000 wafers using 4-nanometer processes by the end of this month. The target is to ramp up production by the first half of 2025, making this facility the most advanced semiconductor fab in the United States.

TSMC’s U.S. fab is facing new challenges as it continues to build and produce concurrently. According to the same report citing industry sources, unlike the previous director-level executive overseeing operations at the U.S. fab, TSMC will be assigning a vice president-level executive to lead the site, with experienced fab construction veteran Arthur Chuang slated for a long-term assignment in the United States starting in May.

Arthur Chuang holds a Ph.D. in Civil Engineering from National Taiwan University and joined TSMC 35 years ago as an equipment engineer. He transitioned to fab operations over 25 years ago and has overseen the construction of nearly 20 fabs, including Fab 15 in Tainan, Fab 18 in Southern Taiwan, and the advanced 2-nanometer fab sites in Hsinchu and Kaohsiung.

TSMC’s second semiconductor fab in the United States is currently under construction, with plans announced on April 8th to commence production of next-generation 2-nanometer process technology in 2028. Additionally, a third fab is scheduled to begin mass production of 2-nanometer or more advanced process technologies by the end of 2030.

The total area of TSMC’s U.S. fab is 1,100 acres, which is more than half of its area in the Hsinchu Science Park. Estimates from the supply chain suggest that this site could accommodate up to six fabs, indicating that TSMC’s expansion plans may go beyond just building a third fab. If collaboration with U.S. partners proceeds smoothly, further expansion is also possible in the future.

TSMC’s Kumamoto Fab Phase 2 to Commence Construction by Year-End, Production Set for 2027

Additionally, TSMC’s Japan Kumamoto Fab (JASM) announced yesterday that its Phase 2 facility will be located adjacent to Phase 1 on the east side, covering an area of approximately 320,000 square meters, which is about 1.5 times the size of Phase 1. Construction is scheduled to commence by the end of this year, with production expected to start by the end of 2027.

TSMC is scheduled to hold an earnings call on April 18th, and ahead of the conference, positive news has emerged regarding the new US fab. It is anticipated that the related topics will also be the focus of attention on the day of the conference.

Read more

• [News] TSMC Receives USD 6.6 Billion for Chipmaking from the US Government, Commits to Constructing Third Fab
• [News] TSMC’s US Fab Reportedly Eyeing for Early Mass Production

(Photo credit: TSMC)

The U.S. government officially announced today that it will provide a USD 6.6 billion subsidy to TSMC, and in its latest press release, confirmed that TSMC will build its third fab in Arizona, USA, with total investment rising to USD 65 billion.

Due to various construction and chip incentive factors, TSMC announced in 2023 that the commissioning of Fab 21 (Fab 1) in Arizona, originally planned for 2024, was postponed to 2025. In January 2024, it was further announced that Fab 2 (originally scheduled to commence operations in 2026) would not begin mass production until 2027 or 2028.

According to the latest information released by TSMC, Arizona’s first fab is on track to begin production leveraging 4nm technology in first half of 2025. The second fab will produce the world’s most advanced 2nm process technology with next-generation nanosheet transistors in addition to the previously announced 3nm technology, with production beginning in 2028.

The third fab will produce chips using 2nm or more advanced processes, with production beginning by the end of the decade. Each of the three fabs, like all of TSMC’s advanced fabs, will have cleanroom area approximately double the size of an industry standard logic fab.

TSMC’s confirmation of plans to build a third fab in Arizona signifies its move towards more advanced semiconductor production in the United States. However, based on the current construction progress in the U.S., market estimates suggest that mass production may not begin until after 2030.

“The CHIPS and Science Act provides TSMC the opportunity to make this unprecedented investment and to offer our foundry service of the most advanced manufacturing technologies in the United States,” said TSMC Chairman Dr. Mark Liu.

“Our U.S. operations allow us to better support our U.S. customers, which include several of the world’s leading technology companies. Our U.S. operations will also expand our capability to trailblaze future advancements in semiconductor technology.”

“We are honored to support our customers who have been pioneers in mobile, artificial intelligence and high-performance computing, whether in chip design, hardware systems or software, algorithms, and large language models,” said TSMC CEO Dr. C.C. Wei.

“They are the innovators driving demand for the most advanced silicon that TSMC can provide. As their foundry partner, we will help them unleash their innovations by increasing capacity for leading-edge technology through TSMC Arizona. We are thrilled by the progress of our Arizona site to date and are committed to its long-term success.”

This market news emerged shortly after the major earthquake in Hualien, Taiwan, leading to speculation within the industry about its connection to the earthquake. Nevertheless, according to industry sources, the recent news about the Fab 3 project in Arizona was not triggered by the recent earthquake but was actually finalized by TSMC after discussions with the U.S. government on future plans.

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• [News] TSMC’s Latest Statement Indicates Equipment Largely Recovered, Revenue Forecast Unchanged
• [News] TSMC’s US Fab Reportedly Eyeing for Early Mass Production

(Photo credit: TSMC)

As TSMC’s earnings call approaches on April 18th, according to a source cited in a report from Commercial Times, it has predicted a downturn in the smartphone industry as it enters a slow season. However, TSMC is reportedly benefiting from AI demand, bolstering its operations through HPC (High-Performance Computing). Additionally, the increasing revenue share from the 3nm process is expected to contribute positively to performance in the second quarter.

TSMC has issued updates for three consecutive days, indicating that the overall recovery rate of its fabs has exceeded 80%. They reiterated their annual performance outlook from January’s earnings call, forecasting revenue growth in the low-to-mid twenties percentage range for the full year. Notably, in the fourth quarter of last year, the revenue share from high-performance computing matched that of smartphones, both reaching 43%, serving as dual engines for operational growth.

The same report, citing sources, indicates that TSMC’s advanced process technology and yield rates lead the industry, making it the primary foundry choice for most global customers.

Based on overall market share, TrendForce’s latest report reveals that in 2023, global foundry revenues hit US$117.47 billion, with TSMC capturing a dominant 60% share. This figure is expected to climb to around $131.65 billion in 2024, increasing TSMC’s share to 62%. It is also estimated in the report from Commercial Times that TSMC holds a market share of approximately 70-80% in 5nm technology, and this is expected to exceed 90% for 3nm, covering nearly all major players in the market.

TSMC has also emphasized that besides traditional smartphone applications, High-Performance Computing (HPC) is becoming an increasingly important application for their advanced processes. This means that even during the second quarter when demand for smartphone chips is typically lower, it will be supported by HPC demand.

The current major AI accelerators such as NVIDIA’s A100 and H100 GPUs, AMD’s Instinct MI250 and MI300, are all manufactured utilizing TSMC’s 7nm or 5nm nodes, highlighting TSMC’s critical position in the AI industry. Reportedly, as demand for AI-based Generative AI (AIGC) continues to rise, TSMC’s production volume is also expected to increase accordingly.

According to the same report citing sources, TSMC’s utilization rate for its 3nm production remains high and unaffected despite the impact of the recent earthquake on its facilities. TSMC has emphasized that key machines used for advanced processes, including all Extreme Ultraviolet (EUV), were undamaged.

However, in areas where the shaking was more severe, certain production lines are expected to require longer adjustments and calibration to restore automated production. TSMC is conducting a comprehensive review of the impact of this earthquake while maintaining close communication with its customers.

Furthermore, TSMC’s biggest challenge at the moment is how to catch up with customer expansion demands.

The most lacking capacity currently is in CoWoS production. Although TSMC maintains its stance of doubling capacity compared to 2023, market estimates cited in the report indicate that TSMC’s capacity is expected to increase from around 13,000 wafers to 30,000-35,000 wafers. This aligns with what founder Morris Chang described—AI chip demand in the future will no longer be in the tens or hundreds of thousands of wafers but will require the capacity of 3, 5, or even 10 fabs.

Read more

• [News] TSMC’s Latest Statement Indicates Equipment Largely Recovered, Revenue Forecast Unchanged
• [News] Taiwan Hit by 7.2 Magnitude Earthquake: TSMC and Other Semiconductor, Panel Supply Chain Updates

(Photo credit: TSMC)