According to wccftech, Intel’s new GPUs will come in two models, namely Battlemage-G10 (abbreviated as BMG-G10) and Battlemage-G21 (abbreviated as BMG-G21).

These two new GPUs from Intel were revealed in an internal document. According to the document, the BMG-G10, targeted at enthusiasts, is a GPU with a TDP of less than 225W, while the BMG-G21 is designed as a mid-range performance product with a maximum TDP not exceeding 150W.

As for specific parameters and performance, the enthusiast-grade BMG-G10 is expected to be equipped with up to 64 Xe2 cores, directly competing with NVIDIA’s RTX 4070. On the other hand, the mid-range BMG-G21 aims at the RTX 4060, both continuing to utilize TSMC’s 4nm manufacturing process.

Therefore, previous rumors suggesting that Intel had canceled the development of BMG-G10 and only retained the BMG-G21 with 40 Xe2 cores appear to be untrue. Moreover, the core count of BMG-G10 is larger than initially reported at 56 Xe2 cores, indicating it is poised to deliver even higher performance.

Recently, per a report from Reuters, Intel, Qualcomm, Google, and other major tech companies are teaming up to challenge NVIDIA’s market dominance and make inroads into the AI software sector. They are expected to look to steer developers away from NVIDIA’s CUDA software platform, a parallel computing platform tailored for GPU acceleration.

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(Photo credit: Intel)

Benefited from frequent orders from its top three clients, Apple, Intel, and AMD, strong momentum has reportedly been driven for TSMC’s 3-nanometer orders, as per a report from Economic Daily News. Anticipated to see sequential growth throughout the year, these orders are expected to remain robust until the end of the year, positioning TSMC as a leader in the semiconductor industry’s recovery.

TSMC has a longstanding policy of not commenting on customer order dynamics. However, it is cited in the report that in the fourth quarter of last year, 3-nanometer orders accounted for approximately 15% of its revenue. With the adoption of 3-nanometer production by major clients this year, revenue from 3-nanometer orders is expected to surpass 20%, becoming the second-largest revenue contributor, following only the 5-nanometer process.

Looking at the orders placed by the top three clients for the 3-nanometer process, Apple is set to introduce the A18 series processor in its iPhone 16 lineup this year. Additionally, the latest self-developed M4 chip for laptops will also be produced by TSMC using the 3-nanometer process, starting in the second quarter.

On the Intel side, the Lunar Lake central processor, graphics processor, and high-speed IO chip are all confirmed to begin mass production at TSMC in the second quarter. This marks Intel’s first instance of outsourcing its entire mainstream consumer platform chip series to TSMC, making it a significant new source of orders for TSMC’s 3-nanometer process this year.

AMD, on the other hand, is poised to unveil its new Zen 5 architecture platform under the code name “Nirvana” this year, expected to significantly enhance AI applications. Following its customary practice, AMD will utilize TSMC’s wafer foundry services, with production set to commence on the 3-nanometer process and an expected launch in the latter half of the year.

TSMC, reportedly, is expanding its production capacity for the 3nm family and advanced packaging this year to meet the large orders from major clients such as Apple, NVIDIA, and AMD in the coming years.

As per TrendForce’s data, the 3nm process alone contributed 6% to TSMC’s Q3 revenue, with advanced processes (≤7nm) accounting for nearly 60% of its total revenue.

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(Photo credit: TSMC)

The US-China tech war continues to escalate, as reported by the Financial Times (FT). Beijing has reportedly instructed official institutions in China to refrain from using PCs and servers equipped with microprocessors from Intel and AMD, as well as to reduce procurement of Microsoft Windows operating systems and database software outside of China.

In response to these reports, both Microsoft and Intel have declined to comment, while AMD, China’s Ministry of Finance, Ministry of Industry and Information Technology, and the China Information Security Evaluation Center have not responded to requests for comment from FT reporters.

FT further reveals that Chinese authorities have requested state-owned enterprises to promote localization internally. Intel and AMD are the two major semiconductor giants in the United States, dominating nearly all global market shares of PC processors.

As both Intel and AMD are significant customers of TSMC’s advanced process nodes, this move is expected to influence TSMC’s future order status. Regarding China’s full-scale development of proprietary computer processors, its potential impact on ASIC-related companies in Taiwan remains to be seen.

As per Industry sources cited by the report, they have suggested that this move by Chinese authorities demonstrates their determination to strengthen local semiconductor autonomy and enhance manufacturing and design capabilities. On the manufacturing side, the focus remains on supporting SMIC, while chip design is primarily led by companies such as Huawei and Phytium.

Per the same report, following the release of new guidelines by China’s Ministry of Finance and Ministry of Industry and Information Technology on December 26th last year, officials have begun adhering to the latest standards for PC, laptop, and server procurement this year. They have mandated that government departments at the township level and above, as well as party organizations, must incorporate standards for purchasing “secure and trustworthy” processors and operating systems.

The China Information Technology Security Evaluation Center has published the first list of “safe and reliable” processors and operating systems, all of which are from Chinese enterprises.

Among the 18 approved processors are chips from Huawei and Phytium. Chinese processor manufacturers are utilizing a hybrid architecture combining Intel x86, Arm, and self-developed designs for chip production, while operating systems are sourced from open-source Linux software.

Prior to the speculated tightening of restrictions by China on the United States, a report from Bloomberg citing sources had already signaled that the US government is considering adding Chinese semiconductor companies linked to Huawei to a blacklist.

Currently, companies that have been listed on the entity list by the US Department of Commerce include Huawei, SMIC (Semiconductor Manufacturing International Corporation), and Shanghai Micro Electronics. Additionally, China’s other major memory manufacturer, Yangtze Memory Technology Corp, was added to this restriction list in 2022.

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(Photo credit: iStock)

As the demand for AI is becoming urgent, according to industry sources cited by the ChinaTimes News, TSMC’s Fab20 P1 plant in Hsinchu’s Baoshan area will undergo equipment installation engineering in April to warm up for mass production of the GAA (gate-all-around) architecture.

Reportedly, it is expected that Baoshan P1, P2, and the three fabs scheduled for advanced process production in Kaohsiung will all commence mass production in 2025, attracting customers such as Apple, NVIDIA, AMD, and Qualcomm to compete for production capacity.

Regarding this rumor, TSMC declined to comment.

Per the industry sources cited by the same report, whether wafer manufacturing is profitable is depending on the yield after mass production. The key lies in the speed at which the yield improves; the longer it takes and the higher the cost, the more challenging it becomes.

As per the same report, TSMC is said to be accelerating its entry into the 2-nanometer realm in April, aiming to shorten the time required for yield improvement in advanced processes. This move not only poses a continuous threat to Samsung and Intel but also widens TSMC’s leading edge.

Industry sources cited by the ChinaTimes’ report have revealed that TSMC has prepared for first tool-in at P1, with trial production expected in the fourth quarter this year and mass production in the second quarter of next year. Equipment manufacturers indicate that they have already deployed personnel and conducted preparatory training in response to TSMC’s customized demands.

As a new milestone in chip manufacturing processes, the 2-nanometer node will provide higher performance and lower power consumption. It adopts Nanosheet technology structure and further develops backside power rail technology. TSMC believes that the 2-nanometer node will enable it to maintain its technological leadership and seize the growth opportunities in AI.

In fact, the cost of producing 2-nanometer chips is exceptionally high. Per the report citing sources, compared to the 3-nanometer node, costs are expected to increase by 50%, with the per-wafer cost reaching USD 30,000. Therefore, the initial adopters are expected to be smartphone chip clients, notably Apple.

Previously, per a report from the media outlet wccftech, Apple’s iPhone, Mac, iPad, and other devices will be the first users of TSMC’s 2nm process. Apple will leverage TSMC’s 2nm process technology to enhance chip performance and reduce power consumption. This advancement is expected to result in longer battery life for future Apple products, such as the iPhone and MacBook.

Unlike with the 3-nanometer node, the complexity of the design means customers must start collaborating with TSMC earlier in the development process. Market speculations suggest that many clients such as MediaTek, Qualcomm, AMD, and NVIDIA have already begun cooperation. TSMC’s earnings call also emphasized that the number of customers for N2 is higher than that for N3 at the same stage of development.

The Fab 20 facility is expected to begin receiving related equipment for 2nm production as early as April, with plans to transition to GAA (Gate-All-Around) technology from FinFET for 2nm mass production by 2025.

The competition in the development of 2-nanometer technology is fierce. ASML plans to produce 10 2-nanometer EUV lithography machines this year, with Intel already reserving 6 of them. Additionally, Japan has mobilized its national efforts to establish Rapidus Semiconductor Manufacturing, which also aims to compete in the 2-nanometer process.

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NVIDIA unveiled its Blackwell architecture and the touted powerhouse AI chip GB200 at GTC 2024 held in San Jose, California, on March 19th. Manufactured using TSMC’s 4-nanometer (4NP) process, it is expected to ship later this year.

According to a report from TechNews, TSMC’s CoWoS technology comes in various forms, including CoWoS-R, CoWoS-L, and CoWoS-S, each differing in cost due to variations in the interposer material. Customers can choose the appropriate technology based on their specific requirements.

CoWoS-R, for instance, integrates InFo technology, utilizing RDL wiring in the interposer to connect chips, making it suitable for high-bandwidth memory (HBM) and SoC integration.

On the other hand, CoWoS-L combines the advantages of CoWoS-S and InFO technologies, offering a cost-effective solution with the use of LSI (Local Silicon Interconnect) chips as the interposer for dense chip-to-chip connections. According to market reports, the Blackwell platform adopts CoWoS-L, as this technology is better suited for larger chiplets.

CoWoS-S, utilizing silicon as the interposer material, represents the highest cost variant and is currently the mainstream choice. Notably, NVIDIA’s H100, H200, and AMD’s MI300 chips all employ CoWoS-S.

NVIDIA’s latest Blackwell architecture features AI chips, including the B100, B200, and the GB200 with Grace CPU, all manufactured on TSMC’s 4-nanometer process. As per the industry sources cited by the report, insights suggest that production for the B100 is slated for the fourth quarter of this year, with mass production expected in the first half of next year.

Meanwhile, the B200 and GB200 are set to follow suit with mass production next year. As per a report from Tom’s Hardware, the AI computing performance of a single B200 GPU can reach 20 petaflops, whereas the previous generation H100 offered a maximum of only 4 petaflops of AI computing performance. The B200 will also be paired with 192GB of HBM3e memory, providing up to 8 TB/s of bandwidth.

TSMC’s advanced manufacturing processes and CoWoS packaging technology are expected to continue benefiting, particularly with the adoption of CoWoS-L packaging.

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(Photo credit: TSMC)