Driven by the AI chip wave, “advanced packaging” emerges as the hottest technology in the semiconductor industry. Its significance extends beyond computational power demands, as the escalating cost of semiconductor processes and the limits of Moore’s Law make the “integration capability” of advanced packaging a crucial weapon for industry players to break through.

According to a report from TechNews, TSMC, Intel, and Samsung have all been deeply involved in advanced packaging for many years and have already introduced corresponding solutions. However, these semiconductor giants are not only focused on this aspect.

In addition to their own technologies, they are actively fostering supply chains, setting standards, and building ecosystems. By accelerating the development of advanced packaging technology, they are also laying the groundwork for their future influence.

Intel, for instance, has chosen to start with standardization by proposing the Universal Chiplet Interconnect Express (UCIe) alliance. Through open specifications and standardized connections, the protocol directly adopts mature standards like PCI Express (PCIe) and the recently developed Compute Express Link (CXL).

The reason for starting with chiplet technology is that in recent years, more and more semiconductor companies have discovered that designing chips using Chiplet architecture and integrating them through advanced packaging technology is more cost-effective than traditional System-on-Chip (SoC) approaches.

Therefore, Intel’s focus on connecting chiplets through standards like UCIe is aimed at providing a standardized interface stack for complete chiplet integration. UCIe supports 2D, 2.5D, and bridge packaging, with future development expected to include support for 3D packaging as well.

Intel’s Packaging Test Technology Development Department’s Senior Chief Engineer, Zhiguo Qian, directly involved in the UCIe Alliance, emphasizes that advanced packaging has become a crucial aspect of semiconductor development, particularly in ensuring the continuation of Moore’s Law.

Qian further points out that when considering the impact of the UCIe standard on the advanced packaging industry, it indeed establishes a standard for interconnecting chiplets within SoCs. This was the original intent behind Intel’s promotion of the UCIe standard alliance.

Currently, advanced packaging is mostly divided into different structures like 2.5D and 3D, and some even classify it as 2.1D or 2.2D, showcasing diverse structural designs across the industry.

However, within these structures, each company has its own proprietary interface solutions, and some even offer multiple solutions. Therefore, to meet customer demands, these standard interconnections must not only be at the forefront of technology but also be compatible with various standards that are open and do not incur any licensing fees.

On the other hand, the UCIe alliance has established various standards, such as the required packaging architectures and interface wiring designs, to achieve the desired performance levels. These standards provide guidelines for customers seeking advanced packaging solutions. By adhering to UCIe standards, customers can anticipate the performance of their chips, without the need for trial and error(in the IC designing stage).

Source: Intel

Currently, companies participating in the UCIe alliance include Qualcomm, AMD, Arm, NVIDIA, TSMC, ASE Group, Winbond Electronics, and Applied Materials, among others, along with semiconductor giants like Samsung. Additionally, Google Cloud, Microsoft, and Meta are members, alongside over 120 other companies.

• TSMC Propels 3D Fabric Alliance

TSMC is also focused on ecosystem development, as evidenced by its announcement of the 3DFabric Alliance within the Open Innovation Platform (OIP) during the 2022 Open Innovation Platform Ecosystem Forum.

In fact, the 3DFabric Alliance is built upon TSMC’s 3DFabric technology introduced in 2020. This technology encompasses a comprehensive solution ranging from advanced processes to silicon stacking and advanced packaging technologies such as CoWoS and InFO.

With an established customer base for its 3DFabric technology, TSMC expanded it into an alliance in 2022. The goal is to assist customers in achieving rapid implementation of chip and system-level innovations while strengthening TSMC’s influence in advanced packaging.

The 3DFabric Alliance marks TSMC’s sixth open innovation platform alliance and is the semiconductor industry’s first alliance aimed at accelerating innovation and enhancing the 3D Integrated Circuit (3D IC) ecosystem in collaboration with partners.

This alliance includes companies in electronic design automation (EDA), silicon intellectual property (IP), design center alliances (DCA)/value chain alliances (VCA), memory, outsourced packaging testing (OSAT), and substrate and testing. Members include Ansys, Cadence, Siemens, ARM, Micron, Samsung, SK Hynix, Amkor, ASE, Advantest, and more.

Source: TSMC

In addition to establishing the alliance, TSMC also introduced the 3Dblox standard during the alliance’s inception. This standard integrates the design ecosystem with validated EDA tools and processes to support 3DFabric technology.

The purpose of this standard is to break the complexity of 3D IC design caused by each EDA supplier using its preferred language. Through the modular 3Dblox standard, key physical stacking and logic connection information in 3D IC design are standardized in a single format, simplifying input and significantly enhancing interoperability among different tools in 3D IC design.

From Intel’s UCIe standard to TSMC’s 3DFabric alliance and 3Dblox standard, it’s evident that in the era of advanced packaging, the key to solidifying the positions and market shares of semiconductor giants lies not only in their individual technological breakthroughs but also in their ability to coordinate and integrate the upstream and downstream industries.

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• [News] The Era of Heterogeneous Integration Approaches: Who Shall Dominate the Advanced Packaging Field?

(Photo credit: TSMC)

According to sources cited by Reuters,  TSMC is reportedly considering plans to establish a production line for its CoWoS technology in Japan. However, TSMC has yet to make any further decisions, and they have declined to comment on the matter.

CoWoS is an advanced packaging technology that stacks chips to enhance computing power, reduce energy consumption, and save space. Currently, TSMC’s CoWoS production capacity is entirely located in Taiwan.

With the booming development of artificial intelligence, global demand for advanced semiconductor packaging has surged, prompting chip suppliers like TSMC, Samsung, and Intel to strengthen their advanced packaging capabilities.

Previously, TSMC’s CEO, C.C. Wei, stated that the company plans to double its CoWoS output by the end of 2024 and further increase it in 2025. With TSMC recently completing the first phase of construction for its Kumamoto fab in Japan and announcing plans for the second phase, which will involve collaboration with Japanese companies SONY Semiconductor Solutions and Toyota Motor Corporation, with a total investment exceeding USD 20 billion and utilizing 6/7-nanometer advanced processes.

However, Joanne Chiao, an analyst at market research firm TrendForce, suggests that if TSMC establishes advanced packaging capacity in Japan, it may face limitations in scale. It remains unclear how much demand there is in Japan for CoWoS packaging, but most of TSMC’s CoWoS customers are currently in the United States.

Additionally, sources cited by Reuters’ report indicate that TSMC’s competitor, Intel, is also considering establishing an advanced packaging research facility in Japan to deepen ties with local chip supply chain companies.

Meanwhile, Samsung, another competitor of TSMC, is setting up advanced packaging research facilities in Yokohama, Japan, with government support. Furthermore, Samsung is in discussions with Japanese and other companies regarding material procurement, preparing to launch its packaging technology similar to that used by SK Hynix.

Regarding the development of the semiconductor industry in Japan, as mentioned in a previous report from TrendForce, Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

However, the looming shortage of semiconductor talent in Japan is a concern. In response, there are generous subsidy programs for talent development. Japan is strategically positioning itself to reclaim its former glory in the world of semiconductors.

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• [News] Subsidies to TSMC from Japan and China Increase Over Fivefold Annually
• [News] High Efficiency in TSMC Kumamoto Plant Construction Sets Stage for Potential Advanced Packaging Investment in Japan

(Photo credit: TSMC)

The Executive Yuan and TSMC have reportedly reached a consensus on the investment project for the new advanced packaging plant at the TSMC Science Park in Chiayi. According to a report from Economic Daily News, six new plant sites will be allocated to TSMC in the Science Park, two more than originally anticipated, with a total investment exceeding NTD 500 billion. The expansion is expected to increase CoWoS advanced packaging capacity and to be announced to the public in early April.

TSMC has refrained from commenting on the matter. Regarding the news, the Executive Yuan actively coordinated with TSMC for the establishment of the advanced packaging plant in the Chiayi Science Park located in Taibao. The related environmental assessments and water and electricity facilities have been processed, with construction expected to commence in April, indirectly confirming the rumors.

As per sources cited by the report, Chiayi Science Park is poised to become a new hub for TSMC’s advanced packaging capacity. Among the six new scheduled plants, construction will begin on two this year, aligning with the Executive Yuan’s statement of construction commencement in April.

TSMC’s extensive expansion is primarily driven by the high demand for advanced packaging. For instance,  in the case of the NVIDIA H100, after integrating components via CoWoS, each wafer yields approximately 28 chips. However, for the upcoming B100, with increased volume and integration, the yield per wafer drops to just 16 chips.

On the other hand, TSMC’s advanced processes, per a previous report from Commercial Times, remained fully utilized, with capacity utilization exceeding 90% in February, driven by sustained AI demand. The same report also noted that NVIDIA’s orders to TSMC are robust, pushing TSMC’s 3 and 4-nanometer production capacity to nearly full utilization.

As each new generation of NVIDIA’s AI chips integrates CoWoS, chip output is halved, yet demand for AI servers continues to soar. With terminal demand skyrocketing while chip output dwindles, there’s a “cliff-like gap” in CoWoS advanced packaging capacity. TSMC must ramp up CoWoS production swiftly to ensure uninterrupted customer supply.

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• [News] SK Hynix Reportedly Invests USD 1 Billion in Advanced Packaging to Strengthen HBM Chip Leadership
• [News] TSMC Reportedly Doubles CoWoS Capacity while Amkor, ASE also Enter Advanced Packaging for AI

(Photo credit: TSMC)

“It is not the shortage of AI chips, it is the shortage of our CoWoS capacity,” replied TSMC Chairman Mark Liu during an interview in September last year, propelling this technology that TSMC had quietly cultivated for over a decade into a global spotlight.

As per a report from TechNews, the hardware demand sparked by generative AI has also led to “advanced packaging” becoming not only a hot keyword pursued by global investors but also a prominent feature of the semiconductor industry. From foundries and memory manufacturers to OASTs, all are actively involved in the research and capacity expansion of advanced packaging technologies.

TSMC, the leading force in the advanced packaging market, has repeatedly emphasized its efforts to expand capacity during its earnings call, including capacity expansions in Zhunan and Hsinchu, and even the possibility of constructing advanced packaging facilities in Chiayi.

Intel’s strategic moves also underscore its emphasis on the development of advanced packaging. Intel’s new plant completed in Penang, Malaysia in 2023 is aimed at establishing advanced packaging capacity.

Leading packaging and testing company, ASE Technology Holding, has also actively participated in the competition for advanced packaging. Apart from its subsidiary, Siliconware Precision Industries (SPIL), which is already a supplier for the backend packaging of CoWoS, ASE Technology Holding is also expanding advanced packaging capacity at its facility in Kaohsiung.

Memory manufacturers are also aggressively ramping up their advanced packaging capacity. SK Hynix, which exclusively supplies HBM for NVIDIA AI chips, recently announced plans to invest USD 1 billion in the development of advanced packaging. They view advanced packaging as the “future focus of semiconductor development for the next 50 years.

Advanced Packaging: Over a Decade of Development

In fact, advanced packaging is not a new concept. Tracing the history of packaging technology, the year 2000 undoubtedly marked a turning point. From this year onwards, packaging technology shifted from traditional wire bonding and flip-chip methods to “wafer-level packaging,” where most or all packaging and testing processes are conducted on the wafer itself.

The 2.5D packaging, which gained significant attention after 2023, actually emerged as early as 2010. However, due to cost concerns, the number of manufacturers adopting this technology was relatively limited, with a focus on high-performance computing chips.

Chiang Shang-yi, the Chief Strategy Officer of Foxconn Semiconductor, recalled the initial lack of interest in CoWoS technology, which even led to him being regarded as a “joke” within the company( TSMC) for proposing advanced packaging. He also revealed that the first company willing to adopt the costly CoWoS technology was actually Huawei.

▲ Semiconductor Packaging Technology Evolution compiled by McKinsey, Accelerated Technological Evolution after 2000 (Source: McKinsey)

Compared to 2D packaging technology, 2.5D packaging involves placing an intermediate layer between the chip and the IC substrate and stacking different chips in parallel. TSMC’s CoWoS has become synonymous with 2.5D packaging, where a silicon interposer layer is inserted between the chip and the SiP substrate, and metal layers are connected using Through-Silicon Vias (TSVs) to overcome the density limitations of SiP substrates, which previously restricted the number of chips.

Despite TSMC’s dominance, Intel, with its extensive technical expertise in CPU packaging, cannot be underestimated. In the 2.5D packaging battlefield, Intel employs EMIB technology as its strategy. Unlike CoWoS, EMIB does not utilize a silicon interposer layer.

Instead, its key feature lies in the “Silicon Bridge,” buried within the packaging substrate, which connects the bare dies. Intel believes that EMIB offers cost advantages compared to solutions using large silicon interposer layers.

In recent years, Samsung, which has been actively cultivating the semiconductor foundry market, has also ventured into the 2.5D packaging arena. Their proprietary I-Cube technology has traditionally targeted applications in High-Performance Computing (HPC) chips. When Samsung introduced I-Cube4 in 2021, it emphasized the integration of multiple logic dies and HBM placed on a silicon interposer layer, enabling heterogeneous integration into a single chip.

As Moore’s Law approaches its limits and the massive computational demands triggered by generative AI continue to surge, coupled with the trend towards lighter, thinner, and smaller end products, chips are inevitably evolving towards more transistors, greater computational power, and lower power consumption performance.

Therefore, the transition of packaging technology from 2.5D to 3D is undoubtedly an inevitable development.

The difference between 3D and 2.5D packaging lies in the stacking method. In 2.5D packaging, chips are stacked parallelly on an intermediate layer, while in 3D packaging, chips are stacked vertically in a three-dimensional manner.

The advantage of 3D packaging lies in its ability to create more space for transistors within a chip through stacking, shorten the distance between different bare dies significantly, enhance transmission efficiency, and reduce power consumption during transmission.

TSMC, Intel, and Samsung Racing for 3D Packaging Technology

TSMC’s positioning in 3D IC technology is undeniable. Its SoIC technology adopts the wafer-to-wafer bonding technique. SoIC integrates homogeneous and heterogeneous small dies into a single chip, with smaller dimensions and a thinner profile. It can be integrated into 2.5D CoWoS or InFO. From an external perspective, SoIC resembles a universal SoC chip but integrates various functions heterogeneously.

Intel’s layout in 3D packaging revolves around its 3D Foveros technology. Structurally, the bottom layer comprises a packaging substrate, with a bottom wafer placed on top serving as an intermediate layer. Within this intermediate layer, numerous TSVs (Through-Silicon Vias) are present, facilitating connections between the upper chips, modules, and other parts of the system to achieve transmission purposes.

Samsung’s X-Cube 3D packaging technology utilizes TSV processes. Currently, Samsung’s X-Cube test chips can stack the SRAM layer on top of the logic layer, interconnected via TSVs, employing its 7nm EUV process technology.

TSMC’s Comprehensive Ecosystem Strategy

Currently dominating the advanced packaging market, thanks to its acquisition of large contracts for manufacturing NVIDIA AI chips, TSMC is not only continuing to develop more advanced packaging technologies but is also actively promoting its 3D Fabric platform.

In addition to incorporating the three key packaging technologies CoWoS, InFo, and SoIC, this platform has expanded into an industry alliance. It includes participation from EDA, IP, DCA/VCA, memory, packaging and testing suppliers, as well as substrate and testing vendors. The goal is to create a complete 3D Fabric ecosystem, strengthen innovation, and enhance customer adoption willingness.

This alliance has attracted active participation from heavyweight players in the semiconductor upstream supply chain. Even companies traditionally seen as competitors in the packaging and testing sector, such as Amkor, ASE Technology Holding, and Siliconware Precision Industries (SPIL), are members. The comprehensive supply chain has become a significant advantage for TSMC in providing advanced packaging contract manufacturing services.

▲ TSMC’s 3D Fabric Alliance members, including major players from EDA to packaging and testing companies. (Image Source: TSMC)

In comparison, Intel, despite its robust technological expertise developed over many years and its proposition to independently provide wafer manufacturing or testing services, faces a disadvantage in expanding its market share in advanced packaging due to its lack of experience in the foundry market.

On the other hand, Samsung, compared to TSMC, is constrained by its yield issues in advanced processes. This limitation leads IC design companies to prioritize foundries with more stable yields when considering outsourcing comprehensive manufacturing services.

Read more

• [News] SK Hynix Reportedly Invests USD 1 Billion in Advanced Packaging to Strengthen HBM Chip Leadership
• [News] TSMC Reportedly Doubles CoWoS Capacity while Amkor, ASE also Enter Advanced Packaging for AI

(Photo credit: TSMC)

Shortly after the release of the MacBook Air with the built-in M3 chip, a report from MacRumors has cited the report that Apple is already working on the development of the next-generation M4 chip, expected to be launched next year.

As per Mark Gurman revealed in a Q&A with Bloomberg, Apple has officially commenced the development of the M4 chip, which is expected to debut alongside the next-generation MacBook Pro. Reportedly, there’s a possibility that the M4 chip may adopt TSMC’s 2nm process. TSMC’s related process is scheduled to undergo first tool-in this year and commence mass production next year.

As per MacRumors’ report, following the introduction of the first in-house developed M1 chip by Apple in November 2020, Apple has consistently pursued chip upgrades. In June 2022, Apple unveiled the M2 chip, followed by the release of the M3 chip at the end of October last year.

With approximately a year and a half gap between each generation of chips, it is speculated by MacRumors that Apple will unveil the M4 chip in the first half of next year. Some sources cited in the report also believe that Apple’s accumulated experience in chip development in recent years may enable them to shorten the development timeline, potentially leading to the announcement of the M4 chip by the end of this year.

However, compared to the 3nm process used in the M3 chip, the 3nm process of the M4 chip could be an upgraded version, with improvements in both computational capability and energy efficiency.

During the earnings call in the fourth quarter of 2023, TSMC announced that its 2-nanometer process (N2) would utilize Nanosheet transistor structures and is anticipated to commence mass production in 2025, so the M4 chip may still adopt the 3nm process.

As for TSMC’s 2-nanometer process, a previous report from wccftech has indicated that Apple is expected to adopt the 2nm process for chip production in the iPhone 17 by 2025.

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• [News] The Imminent Arrival of 2-Nanometer Advanced Process
• [News] Apple Reportedly Places Large Orders for TSMC’s 3nm While Simultaneously Securing Significant Advanced Packaging Capacity

(Photo credit: Apple)