Shortly after the release of the MacBook Air with the built-in M3 chip, a report from MacRumors has cited the report that Apple is already working on the development of the next-generation M4 chip, expected to be launched next year.

As per Mark Gurman revealed in a Q&A with Bloomberg, Apple has officially commenced the development of the M4 chip, which is expected to debut alongside the next-generation MacBook Pro. Reportedly, there’s a possibility that the M4 chip may adopt TSMC’s 2nm process. TSMC’s related process is scheduled to undergo first tool-in this year and commence mass production next year.

As per MacRumors’ report, following the introduction of the first in-house developed M1 chip by Apple in November 2020, Apple has consistently pursued chip upgrades. In June 2022, Apple unveiled the M2 chip, followed by the release of the M3 chip at the end of October last year.

With approximately a year and a half gap between each generation of chips, it is speculated by MacRumors that Apple will unveil the M4 chip in the first half of next year. Some sources cited in the report also believe that Apple’s accumulated experience in chip development in recent years may enable them to shorten the development timeline, potentially leading to the announcement of the M4 chip by the end of this year.

However, compared to the 3nm process used in the M3 chip, the 3nm process of the M4 chip could be an upgraded version, with improvements in both computational capability and energy efficiency.

During the earnings call in the fourth quarter of 2023, TSMC announced that its 2-nanometer process (N2) would utilize Nanosheet transistor structures and is anticipated to commence mass production in 2025, so the M4 chip may still adopt the 3nm process.

As for TSMC’s 2-nanometer process, a previous report from wccftech has indicated that Apple is expected to adopt the 2nm process for chip production in the iPhone 17 by 2025.

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• [News] The Imminent Arrival of 2-Nanometer Advanced Process
• [News] Apple Reportedly Places Large Orders for TSMC’s 3nm While Simultaneously Securing Significant Advanced Packaging Capacity

(Photo credit: Apple)

With AI demand exploding across the board, TSMC initiated a major expansion plan for CoWoS in 2023. According to MoneyDJ citing sources, TSMC reportedly initiated a new wave of orders to Taiwan-based equipment manufacturers this month. Delivery is expected in the fourth quarter of this year.

Therefore, by the end of 2024, monthly production capacity may have the chance to double from the company’s target and further exceed market estimates of 35,000 wafers, possibly reaching over 40,000 wafers. As per the same report, TSMC is making a full-scale push to expand its CoWoS production capacity, aiming for a doubling of growth by 2024, with continued expansion expected in 2025.

As per multiple sources cited by MoneyDJ, TSMC resumed ordering CoWoS equipment in April 2023, with the second and third waves of additional orders placed in June and October, respectively. Subsequently, there were sporadic additional orders.

However, this month, there is a new wave of proactive orders, scheduled for delivery in the fourth quarter. Initially, it was estimated that CoWoS monthly production capacity would reach 32,000 to 35,000 wafers by the end of 2024. Now, it is possible that it will exceed 40,000 wafers.

Regarding TSMC’s SoIC, following AMD, Apple also plans to adopt this technology, intending to use SoIC combined with Hybrid molding. Currently, it is undergoing small-scale trial production.

To meet customer demand, TSMC continues to revise its capacity plans. At the end of last year, SoIC monthly capacity was around 2,000 wafers, with a target to reach nearly 6,000 wafers by the end of this year. The monthly capacity target for 2025 is to double again to over 14,000 to 15,000 wafers.

Still, as per industry sources cited by CNA in its previous report, the demand for advanced packaging capacity for AI chips still outstrips supply. The report also revealed that NVIDIA has sought assistance from packaging and testing subcontractors outside of TSMC to augment their advanced packaging capabilities.

Amkor, among others, began gradually providing capacity support from the fourth quarter of last year, while SPIL, a subsidiary of ASE, is slated to commence supply in the first quarter of this year.

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• [News] TSMC to Expand Production with New Facilities Across Taiwan in April
• [News] TSMC Reportedly Doubles CoWoS Capacity while Amkor, ASE also Enter Advanced Packaging for AI

(Photo credit: TSMC)

As various governments actively court semiconductor foundries in Taiwan, PSMC, in partnership with India’s Tata Group, held a groundbreaking ceremony for India’s first 12-inch fab on March 12th. As per a report from TechNews, PSMC has been collaborating with Japan and India recently to establish a semiconductor manufacturing path distinct from TSMC’s, marking Chairman Frank Huang’s latest overseas strategy amidst geopolitical shifts.

Due to various countries actively developing the semiconductor industry and seeking assistance from Taiwan, PSMC Chairman Frank Huang stated that this year is a transformative year for PSMC. In addition to optimistically viewing the new foundry opportunities brought about by geopolitical shifts, PSMC will also focus on a global development strategy centered around “Fab IP.”

“Taiwan’s semiconductor strength is formidable because no one else can do what Taiwan is doing,” said Frank Huang. He mentioned that, following President Tsai Ing-wen’s directive to assist India in building a semiconductor plant, it serves as a path for Taiwanese companies to understand the foundational cooperation model in India.

Therefore, PSMC decided to provide technology, with India responsible for building the plant and providing funding. The investment structure involves 70% from the Indian government and 30% from the Tata Group.

Global Expansion Through “Fab IP”

PSMC’s Fab IP strategy leverages its long-term accumulated experience in plant construction and semiconductor manufacturing technology to assist other countries in building semiconductor plants while earning royalties for technology transfers.

Frank Huang pointed out that the company has established a “Manufacturing IP Transfer Department” which does not invest money but only provides technology transfer. Its main focus is assisting other countries in building plants, extending from Japan and India to countries in the Middle East and Europe, all of which represent opportunities for Taiwan.

PSMC General Manager Brian Shieh believes that overseas plant construction requires a thorough consideration of operations and future costs. Therefore, PSMC tends to assist in building plants without assuming operational responsibilities. Instead, they only provide services, which differs from TSMC’s overseas cooperation model.

Due to the keen interest of various countries in IP technology transfer, Frank Huang believes that IP transfer will also become one of the important sources of revenue in the future. “Up to 7-8 countries have approached PSMC,” including Vietnam, Thailand, India, Saudi Arabia, France, Poland, Lithuania, and others.

He mentioned that from Japan to India, they have been actively engaged in IP transfer and are currently in discussions with two other countries. The source cited by the report also indicates that Vietnam is actively negotiating with PSMC, although PSMC has not responded to this.

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• [News] PSMC Assists Tata in Fab Establishment through Technology Transfer
• [News] Tata Group Rumored to Invite Taiwanese Businesses to Establish Fabs in India, Possibly Partnering with UMC or PSMC

(Photo credit: PSMC)

Recently, IC design company Marvell announced an expansion of its long-term partnership with TSMC to include 2-nanometer technology. They will collaborate on developing the industry’s first 2-nanometer semiconductor production platform optimized for accelerating infrastructure.

Currently, the most advanced production technology in the industry is the 3-nanometer process, manufactured by Samsung Electronics and TSMC. With Intel securing the first ASML lithography machine and updating its latest manufacturing roadmap, and with the increasing collaboration between Rapidus and IBM, the competition for the 2-nanometer advanced process has significantly expanded to include TSMC, Intel, Samsung and  Rapidus.

• Marvell

According to Marvell’s press release, it has stated that Marvell has transitioned from a follower to a leader in integrating advanced node technology into silicon infrastructure.

Marvell first bringing advanced node technology to infrastructure silicon with its 5nm platform, followed by the release of several 5-nanometer designs and the profolio of the first silicon infrastructure product lineup based on TSMC’s 3-nanometer process.

“Tomorrow’s artificial intelligence workloads will require significant and substantial gains in performance, power, area, and transistor density. The 2nm platform will enable Marvell to deliver highly differentiated analog, mixed-signal, and foundational IP to build accelerated infrastructure capable of delivering on the promise of AI,” said Sandeep Bharathi, chief development officer at Marvell.

• TSMC

TSMC commenced mass production of its 3-nanometer process in 2022, with profitability realized starting from the third quarter of 2023. By the fourth quarter of 2023, the 3-nanometer process contributed to 15% of wafer revenue, and its revenue share has been steadily increasing.

According to TrendForce, the foundry market is expected to grow by 7% in 2024, largely attributed to TSMC’s ramp-up of its 3-nanometer process. This has further increased TSMC’s market share.

During the earnings call in the fourth quarter of 2023, TSMC announced that its 2-nanometer process (N2) would utilize Nanosheet transistor structures. It is anticipated that N2 will commence mass production in 2025, leading the industry in terms of density and energy efficiency.

The N2 backside power delivery solution is slated for release in the latter half of 2025 and is expected to enter mass production in 2026, primarily targeting the High-Performance Computing (HPC) sector.

Furthermore, due to the current high demand for 2-nanometer processes from all AI innovators worldwide surpassing that for 3-nanometer processes, almost all AI innovators are collaborating with TSMC on 2-nanometer process technology. The main applications are primarily focused on high-performance computing (HPC) and smartphones.

Consequently, TSMC has announced plans to expand its production capacity for 2-nanometer processes. Originally, two 2-nanometer fabs were planned for the Kaohsiung facility, but now consideration is being given to constructing a third 2-nanometer fab.

• Samsung

Samsung commenced mass production of its 3-nanometer process in June 2022. According to the latest industry reports, Samsung has developed a “second-generation 3-nanometer” process, renamed as “2-nanometer”, with plans for mass production before the end of this year.

At the 2023 Samsung Foundry Forum, Samsung Electronics unveiled the latest roadmap for its 2-nanometer process. Samsung Electronics President and Head of Foundry Business, Siyoung Choi, disclosed that Samsung will first mass-produce 2-nanometer chips for mobile terminals starting from 2025. Subsequently, in 2026, the technology will be applied to high-performance computing (HPC) products, followed by expansion to automotive chips by 2027.

Unlike TSMC, which opted for Gate-All-Around (GAA) structure at the outset of its 2-nanometer process, Samsung has been utilizing GAA structure since its 3-nanometer process. This suggests that Samsung may have more experience in new structures compared to TSMC, thus giving Samsung an advantage in its 2-nanometer node.

In the past, when Samsung Electronics transitioned from 7-nanometer to 5-nanometer process technology in 2020, the second generation 7-nanometer process technology was renamed as 5-nanometer process technology.

Samsung Electronics’ 7-nanometer process technology became the world’s first to use Extreme Ultraviolet (EUV) lithography in 2019, making it more stable and enabling the company to further shrink transistor sizes. This was also the reason for renaming the second generation 7-nanometer process to 5-nanometer process at that time.

A report from the Business Korea has indicated that Samsung Electronics recently secured an order from the Japanese AI startup Preferred Networks (PFN) to produce semiconductors based on the 2-nanometer process.

It is reported that PFN has been collaborating with TSMC since 2016, but this year, it has decided to produce the next generation of AI chips at Samsung’s 2-nanometer node. According to the agreement, Samsung will utilize its latest 2-nanometer chip fab technology to manufacture AI accelerators and other AI chips for PFN.

• Intel

As per Intel’s previously announced plans, the company aims to catch up with and surpass TSMC by 2024 or 2025. At this year’s “Direct Connect” conference hosted by Intel Foundry Services, the company unveiled its latest technological roadmap.

Intel has reported that its primary product, Clearwater Forest, which is under the 18A process, has been completed and is set for production in 2025. Intel’s 18A process is often compared with TSMC’s N2 (2-nanometer) and N3P (3-nanometer) processes in terms of performance, with each company advocating for its own advantages.

Intel CEO Pat Gelsinger emphasizes that both 18A and N2 utilize GAA transistors (RibbonFET), but the 1.8-nanometer node will adopt BSPND, a backside power delivery technology that optimizes power and clock. TSMC, on the other hand, believes that its N3P (3-nanometer) technology will rival Intel’s 18A in power consumption, performance, and area (PPA), while its N2 (2-nanometer) will surpass it in all aspects.

Additionally, Intel’s 20A manufacturing technology is reportedly scheduled for launch in 2024, introducing two technologies: RibbonFET surround gate transistors and backside power delivery network (BSPDN). These aim to achieve higher performance, lower power consumption, and increased transistor density.

Meanwhile, Intel’s 18A production node aims to further refine the innovations of 20A and provide additional PPA improvements from late 2024 to early 2025. Per Intel’s statements regarding its fab processes, its 2-nanometer technology is expected to be the earliest to debut.

Of particular note, Intel announced for the first time at the conference the development of 14A (1.4nm) and its evolutionary version, 14A-E. Intel’s 14A process is the industry’s first node to utilize ASML High-NA EUV lithography tools, making Intel the first company in the industry to acquire cutting-edge High-NA tools. Intel expects to develop 14A by 2027.

• Rapidus

In addition to the aforementioned semiconductor foundries, a Japanese company, Rapidus, is worth noting as well. Established in August 2022, Rapidus was jointly founded by eight Japanese companies including Toyota, Sony, NTT, NEC, SoftBank, Denso, NAND Flash giant Kioxia, and Mitsubishi UFJ.

On January 22nd of 2024, Rapidus President Junichi Koike announced during a press conference that construction of the Rapidus 2-nanometer chip fab in Japan is progressing smoothly, and the trial production line is scheduled to commence operations in April 2025 as planned. Additionally, there are plans for the construction of a second and third facility in the future.

In September of last year, Rapidus began construction of Japan’s first logic chip fab, “IIM-1,” in Chitose City, Hokkaido, capable of producing chips below 2 nanometers. It is reported that the fab is expected to be completed by December of this year.

Previously, Rapidus signed a collaboration agreement with IBM to develop technology based on IBM’s 2-nanometer process. IBM had already introduced the world’s first 2-nanometer process chip back in 2021. Similarly, IBM’s 2-nanometer process also utilizes GAA (Gate-All-Around) structure. This partnership provides Rapidus with the technical support necessary for advanced process development.

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• [News]The 2nm Semiconductor Foundry Race Between TSMC, Samsung, Rapidus Begins with an Equipment Battle

(Photo credit: TSMC)

Taiwan’s residential and industrial electricity prices have long ranked among the lowest globally, but, as per CNA’s report, to stabilize Taiwan Power Company’s finances, electricity price hikes in April are nearly finalized. Among these adjustments, industrial electricity rates will vary based on the specific industry’s consumption patterns.

Under the current plan, residential and general industrial electricity will be categorized into three tiers, each subject to different price adjustments. As for the “super consumers” in the high-voltage category (defined as those with over 5 billion kilowatt-hours consumed annually for two consecutive years), the rate hike could reach up to 30 percent, impacting major consumers in the semiconductor firms like TSMC and Micron.

As per the report from Taiwanese media NowNews, market concerns are mounting over the 24-hour operations of semiconductor fabs. Despite the potential for energy savings through “time-based electricity pricing,” the effectiveness of such measures may be limited. This could significantly escalate operating costs for companies.

Regarding the potential impact of electricity price adjustments on the semiconductor industry, Taiwanese Minister of Economic Affairs Mei-Hua Wang recently stated that even with 24-hour electricity usage, TSMC maintains high energy efficiency. Moreover, semiconductor fabs primarily export their products after manufacturing. Compared to fabs in other countries, Taiwan’s electricity prices are still relatively low.

The definition of high-voltage super consumers entails annual electricity usage exceeding 5 billion kilowatt-hours, with consecutive growth over two years. Different companies will be distinguished within this category. Semiconductor manufacturers, as well as data centers, will be included in the high-voltage super consumer classification.

However, the rate hike of electricity prices for these significant consumers will depend on the subsidy budget allocated by the Executive Yuan. If a subsidy of TWD 100 billion (roughly USD 3.2 billion)  is allocated, the rate hike could exceed 30%. Even with a subsidy of TWD 150 billion (roughly USD 4.8 billion) , the increase would still surpass 20%.

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• [News] TSMC to Expand Production with New Facilities Across Taiwan in April

(Photo credit: TSMC)