South Korean memory giant SK Hynix has confirmed record-breaking sales of High Bandwidth Memory (HBM) over the past few months, driving profitability in the fourth quarter and predicting an industry-wide recovery.

According to Wccftech, SK Hynix Vice President Kim Ki-tae stated on February 21st that the demand for HBM, as an AI memory solution, is experiencing explosive growth as generative AI services become increasingly diverse and continue to evolve.

The report has cited insights from Kim Ki-tae, who stated, “HBM, with its high-performance and high-capacity characteristics, is a monumental product that shakes the conventional wisdom that memory semiconductors are only a part of the overall system. ”

Kim Ki-tae also mentioned that despite ongoing external uncertainties, the memory market is expected to gradually warm up in 2024. This is attributed to the recovery in product demand from global tech giants.

Moreover, AI devices such as PCs or smartphones are expected to increase the demand for artificial intelligence. This surge is anticipated to boost the sales of HBM3E and potentially drive up the demand for products like DDR5 and LPDDR5T.

Kim Ki-tae emphasized that their HBM products have already sold out for this year. Although it’s just the beginning of 2024, the company has already begun gearing up for 2025.

SK Hynix Plans to Establish Advanced Packaging Plant in the US

SK Hynix is reportedly set to establish an advanced packaging plant in Indiana, with the US government aiming to reduce dependence on advanced chips from Taiwan.

As per the Financial Times on February 1st, citing unnamed sources, SK Hynix’s rumored new packaging facility in Indiana may specialize in 3D stacking processes to produce HBM, which will also be integrated into NVIDIA’s GPUs.

Currently, SK Hynix produces HBM in South Korea and then ships it to Taiwan for integration into NVIDIA GPUs by TSMC.

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(Photo credit: SK Hynix)

Pat Gelsinger, CEO of Intel, announced on February 22nd that Intel will expand its orders to TSMC, as per a report by Commercial Times.

Following the IFS Direct Connect event in San Jose, USA, Gelsinger pointed out in an interview that two generations of CPU Tiles would be manufactured using TSMC’s N3B process,  marking the official arrival of Intel CPU orders for laptop platforms. 

Gelsinger’s interview confirms that Intel has indeed expanded its outsourcing orders to TSMC. Currently, TSMC is responsible for producing Intel CPUs, GPUs, and NPUs tiles for the Arrow and Lunar Lake platforms.

As per Intel’s product roadmap, Arrow Lake will utilize the Intel 20A process, while Lunar Lake will utilize the 18A process, both incorporating transistor designs such as PowerVia and RibbonFET.

Gelsinger previously stated that Intel Foundry is striving to become the world’s second-largest foundry by 2030. The objective is to fill the fabs and supply the widest range of customers globally, including competitors like NVIDIA and AMD.

According to TrendForce’s data statistics for the third quarter of 2023, the world’s top three foundries were TSMC, Samsung, and GlobalFoundries, with Intel Foundry Services (IFS) ranking ninth at the time.

As for rumors about the US government considering providing over USD 10 billion in subsidies, he disclosed that they expect to receive chip legislation subsidies very soon, although the exact amount is yet to be announced.

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(Photo credit: Intel)

Kevin Zhang, Senior Vice President of Business Development at TSMC, introduced the company’s latest technologies at the International Solid-State Circuits Conference (ISSCC) 2024. According to TechNews citing from the speech, Zhang shared insights into future technological advancements, prospects for advanced processes, and the latest semiconductor technologies needed in various fields.

Zhang noted that since the introduction of ChatGPT and Wi-Fi 7, a lot of advanced semiconductor are required, as we are entering an accelerated growth period for semiconductor going forward.

In the automotive sector, the industry is undergoing a revolution, with many suggesting that new vehicles will be software-defined. However, Zhang believes it’s more about silicon-defined because software needs to run on silicon, driving the future of autonomous driving capabilities.

CFET (Complementary Field-Effect Transistor)

In terms of technology, Transistor remain at the heart of the innovation, silicon innovation. It has shifted from geometry reduction to architectural innovation and the use of new materials. Moving from 16-nanometer FinFET to today’s 2-nanometer Nano Sheet technology represents significant progress in high-performance computing and architectural innovation.

What’s next? The answer is CFET.

Kevin Zhang explained that CFET involves stacking nMOS and pMOS on top of each other, significantly improving component currents and increasing transistor density by 1.5 to 2 times.

Alternatively, efforts are being made to create higher-performance switching devices from low-dimensional materials such as 2D materials, surpassing today’s devices or transistors.

Kevin Zhang also showcased that TSMC has successfully fabricated CFET architectures in the laboratory, stating, “This is a real integrated device that has been fabricated in our lab. Here, you see the transistor IV curve. They are beautiful curves. So, this is a significant milestone in terms of continuing to drive the innovation of the transistor architecture.”

However, as the geometry of the transistor shrinks, it becomes increasingly difficult and costly. This necessitates collaboration between process development teams and design research to achieve optimal benefits, known as “Design-Technology Co-Optimization” (DTCO).

In addition, TSMC has introduced FINFLEX technology, enabling chip designers to choose and mix the best fin structures to support each critical functional block, achieving optimal performance, density, and power consumption.

Another example of DTCO is Static Random Access Memory (SRAM). SRAM has scaled from 130 nanometers to the current 3 nanometers, and TSMC has achieved a over 100x density improvement, a result of collaboration or combination of a process innovation and adoption of the more advanced design technique.

Nevertheless, the essence or the objective of this technology scaling is for “energy efficient compute,” as Kevin Zhang expressed. He stated that in the entire semiconductor industry, TSMC has come a long way, and this progress has made today’s AI possible.

• Advancements in HPC/AI Technology Platforms: 3D Stacking, Silicon Photonics, CPO

Whether it’s GPUs, TPUs, or customized ASICs, they all feature this particular integration scheme. Currently, the mainstream is 2.5D packaging. However, to meet future high-performance computing demands, this platform needs significant enhancement, requiring higher density and lower power consumption computation.

Therefore, stacking is needed, including integrating many memory bandwidths and HBM into the package, while considering issues such as power supply, I/O, and interconnect density.

Consequently, Kevin Zhang stated that bringing “silicon photonics into packaging” is the future direction. However, this will face many challenges, such as Co-Packaged Optics (CPO) closer to the electronic side.

1. 3D Stacking

When it comes to 3D stacking, Kevin Zhang presented a diagram and explained that to achieve higher interconnect density, specifically Chip-to-Chip connections, 3D stacking allows the bonding pitch to scale to just a few micrometers, achieving interconnect density like monolithic. “That’s why the 3D (stacking) is the future,” he concluded.

2. Silicon Photonics / Co-Packaged Optics (CPO)

Kevin Zhang pointed out that while electronics excel at computation, photons are better for signaling or communication. He illustrated that if a 50 terabyte switch, an all-electronic copper system were used, it would consume 2,400 W.

The current solution involves using pluggable modules, which can save 40% of power (> 1500W). However, as the need for higher-speed signals and larger bandwidths increases in the future, this solution falls short. Therefore, integrating silicon photonics technology is necessary to introduce photon capabilities.

• Automotive Technology

1. Pursuing Low DPPM

Fundamentally, the latest automotive technologies require significant computational power, but power consumption is becoming a concern, especially for battery-powered vehicles.

Kevin Zhang states that automotive semiconductor technology has lagged behind consumer or HPC technologies by several generations due to stringent safety requirements. The DPPM (Defects Per Million) for automotive applications must be close to zero.

Therefore, fabs, semiconductor manufacturers, and automotive designers must collaborate more closely to accelerate this pace. He also promises, “you will see 3 nanometer in your car before long.”

2. MRAM/RRAM

As automotive transitions to a domain architecture, MCUs (Microcontroller Units) become increasingly important and require advanced semiconductor technology to provide computational capabilities.

Traditional MCUs mostly rely on floating-gate technology, but this technology encounters bottlenecks below 28 nanometers. Fortunately, the industry has invested in new memory technologies, including new non-volatile memories such as Magnetic Random Access Memory (MRAM) or Resistive Random Access Memory (RRAM).

Therefore, transitioning from MCU to MRAM or RRAM-based technologies helps drive continuous technology scaling from 28 nanometers to 16 nanometers, or even 7 nanometers.

• Sensor and Display: CIS (CMOS Image Sensors)

Sensor technology has evolved from simple 2D designs and single layer design to intelligent systems with 3D wafer stacking, essentially layering the signal processing on top of the sensing layer.

Kevin Zhang also mentioned, “our technologies already start investing, researching on the multi-layer design.”

Engaging in three or more layer designs allows for the optimization of pixels, continuing the trend of scaling pixel sizes while meeting resolution requirements and achieving optimal sensing capabilities simultaneously.

Another example is AR (Augmented Reality) and VR (Virtual Reality), where separating memory layers and stacking them onto other logic chips can effectively reduce size while maintaining high-performance demands.

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(Photo credit: TSMC)

Despite challenges, Samsung Semiconductor remains optimistic about the market outlook for the second half of the year. According to a report from TechNews citing sources , to compete with TSMC and enhance efficiency to meet market demands, Samsung is reportedly adjusting the expansion schedule of its fabs.

As per a report from global media outlet SamMobile, Samsung Semiconductor is adjusting the construction schedule of its Pyeongtaek Plant 4 (P4) in South Korea to prioritize the construction of the PH2 production line, temporarily halting the construction of the new production line at the semiconductor plant 5 (P5).

In addition, Samsung is said to be reallocating resources to invest in the PH2 production line at the P4 plant. Once the cleanroom is completed, it will be dedicated to contract chip manufacturing.

Pyeongtaek is a major semiconductor manufacturing center for Samsung, serving as a significant hub for its foundry business and a crucial memory plant. South Korea’s Pyeongtaek currently has the operational P1, P2, and P3 plants, with the construction of the P4 and P5 underway.

Reportedly, Samsung is expected to expand its contract manufacturing capacity to secure more clients from its competitor, TSMC. Additionally, the P4 plant will also establish the PH3 production line to produce DRAM and other components. Samsung’s adjustment in plans reflects its anticipation of rising market demand and its efforts to prepare to meet those demands.

While Samsung stated that the suspension of the P5 plant was for inspection purposes, sources cited in the SamMobile report believe that Samsung likely slowed down the progress of the P5 plant due to the previous downturn in the semiconductor market.

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(Photo credit: Samsung)

TSMC is scheduled to hold the opening ceremony for its Kumamoto plant on February 24. In contrast, the construction progress of its Arizona plant in the United States has been relatively slow.

According to TechNews citing a research report from the Center for Security and Emerging Technology (CSET), the construction speed of semiconductor plants in the United States is the slowest globally due to the intricate regulatory environment. While the U.S. chip law supports the semiconductor industry, it is insufficient to address construction costs and timelines.

Looking at the construction speed of the three major foundries in the United States, they have indeed all fallen behind their original targets. For instance, TSMC’s Arizona plant was delayed by a year, Intel’s Ohio plant was pushed from 2025 to the end of 2026, and Samsung’s Texas plant, due to not receiving chip bill subsidies, was also delayed to 2025.

As per research conducted by CSET on the construction of 635 semiconductor plants from 1990 to 2020, the average time from groundbreaking to production was 682 days globally. However, in the United States, the average was 736 days, significantly higher than the global average and second only to Southeast Asia’s 781 days.

In comparison, the construction speeds in Taiwan, South Korea, and Japan are 654 days, 620 days, and 584 days, respectively, with Japan’s performance being quite remarkable. As for Europe and the Middle East, the average is 690 days, while in China, it is 701 days.

The report further indicates that in the 1990s and 2000s, foundries in the United States had a relatively faster construction speed, with an average time of about 675 days. However, by the 2010s, this time frame extended to 918 days.

Meanwhile, during the same period, the construction speed in China and Taiwan significantly accelerated, with average completion times of 675 days and 642 days, respectively.

Furthermore, the number of foundries in the United States has been declining, from 55 in the 1990s to 43 in the 2000s and 22 in the 2010s. In contrast, the construction speed of foundries in China has significantly accelerated, from 14 in the 1990s to 75 in the 2000s, and further to 95 in the 2010s.

Although China’s semiconductor technology is still in the catch-up phase, the construction of foundries positions it as a dominant force in the industry.

Stringent Regulations in the United States Lead to Slow Factory Construction Despite Favorable Conditions 

The report highlights seven key requirements for foundry construction: Large plots of land, low seismic activity, stable water supply, stable supply of electricity, talent, transportation infrastructure, and nearby land for co-location with key suppliers.

In these aspects, the United States outperforms Taiwan; however, the primary obstacle is regulatory issues.

Due to the unique federal structure of the United States, foundry construction must comply with federal, state, and local regulations, resulting in an exceptionally complex regulatory process. Additionally, environmental policies pose obstacles to foundry construction, particularly due to stringent requirements for environmental protection

The report suggests that to enhance the United States’ competitiveness in the global semiconductor industry, the government needs to streamline regulatory processes, eliminate redundant regulations, and establish expedited pathways to accelerate semiconductor industry construction projects.

Additionally, there should be an acceleration of environmental review processes and investment in the development of alternative materials to ensure sustainable semiconductor material supplies.

With the continued growth in global semiconductor demand, the construction speed and efficiency of US semiconductor fabs will directly impact its position in the global market.

To maintain its leading position, per the report, the United States urgently needs to take action to address this issue. Currently, it is unclear how much impact the delayed construction of semiconductor fabs by TSMC, Intel, and Samsung will have.

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(Photo credit: TSMC)