TSMC is scheduled to hold the opening ceremony for its Kumamoto plant on February 24. In contrast, the construction progress of its Arizona plant in the United States has been relatively slow.

According to TechNews citing a research report from the Center for Security and Emerging Technology (CSET), the construction speed of semiconductor plants in the United States is the slowest globally due to the intricate regulatory environment. While the U.S. chip law supports the semiconductor industry, it is insufficient to address construction costs and timelines.

Looking at the construction speed of the three major foundries in the United States, they have indeed all fallen behind their original targets. For instance, TSMC’s Arizona plant was delayed by a year, Intel’s Ohio plant was pushed from 2025 to the end of 2026, and Samsung’s Texas plant, due to not receiving chip bill subsidies, was also delayed to 2025.

As per research conducted by CSET on the construction of 635 semiconductor plants from 1990 to 2020, the average time from groundbreaking to production was 682 days globally. However, in the United States, the average was 736 days, significantly higher than the global average and second only to Southeast Asia’s 781 days.

In comparison, the construction speeds in Taiwan, South Korea, and Japan are 654 days, 620 days, and 584 days, respectively, with Japan’s performance being quite remarkable. As for Europe and the Middle East, the average is 690 days, while in China, it is 701 days.

The report further indicates that in the 1990s and 2000s, foundries in the United States had a relatively faster construction speed, with an average time of about 675 days. However, by the 2010s, this time frame extended to 918 days.

Meanwhile, during the same period, the construction speed in China and Taiwan significantly accelerated, with average completion times of 675 days and 642 days, respectively.

Furthermore, the number of foundries in the United States has been declining, from 55 in the 1990s to 43 in the 2000s and 22 in the 2010s. In contrast, the construction speed of foundries in China has significantly accelerated, from 14 in the 1990s to 75 in the 2000s, and further to 95 in the 2010s.

Although China’s semiconductor technology is still in the catch-up phase, the construction of foundries positions it as a dominant force in the industry.

Stringent Regulations in the United States Lead to Slow Factory Construction Despite Favorable Conditions 

The report highlights seven key requirements for foundry construction: Large plots of land, low seismic activity, stable water supply, stable supply of electricity, talent, transportation infrastructure, and nearby land for co-location with key suppliers.

In these aspects, the United States outperforms Taiwan; however, the primary obstacle is regulatory issues.

Due to the unique federal structure of the United States, foundry construction must comply with federal, state, and local regulations, resulting in an exceptionally complex regulatory process. Additionally, environmental policies pose obstacles to foundry construction, particularly due to stringent requirements for environmental protection

The report suggests that to enhance the United States’ competitiveness in the global semiconductor industry, the government needs to streamline regulatory processes, eliminate redundant regulations, and establish expedited pathways to accelerate semiconductor industry construction projects.

Additionally, there should be an acceleration of environmental review processes and investment in the development of alternative materials to ensure sustainable semiconductor material supplies.

With the continued growth in global semiconductor demand, the construction speed and efficiency of US semiconductor fabs will directly impact its position in the global market.

To maintain its leading position, per the report, the United States urgently needs to take action to address this issue. Currently, it is unclear how much impact the delayed construction of semiconductor fabs by TSMC, Intel, and Samsung will have.

Read more

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(Photo credit: TSMC)

The surge in demand for advanced packaging is being primarily propelled by artificial intelligence (AI) chips. According to industry sources cited by CNA, TSMC’s CoWoS production capacity is set to double this year, yet demand continues to outstrip supply. In response, NVIDIA has enlisted the help of packaging and testing facilities to augment its advanced packaging capabilities.

In addition, to address the imbalance between supply and demand for advanced packaging due to AI, semiconductor backend specialty assembly and testing (OSAT) companies such as ASE Technology Holding (ASE), Powertech Technology, and KYEC have expanded their capital expenditures this year to enhance their advanced packaging capabilities, aligning with the needs of their customers.

AI and high-performance computing (HPC) chips are driving the demand for CoWoS advanced packaging. As per sources interviewed by CNA, from July to the end of last year, TSMC actively adjusted its CoWoS advanced packaging production capacity, gradually expanding and stabilizing mass production.

The source further indicates that in December of last year, TSMC’s CoWoS monthly production capacity increased to 14,000 to 15,000. It is estimated that by the fourth quarter of this year, TSMC’s CoWoS monthly production capacity will significantly expand to 33,000 to 35,000.

Per an earlier report from Commercial Times, TSMC has been outsourcing part of its CoWoS operations for some time, mainly targeting small-volume, high-performance chips. TSMC maintains in-house production of the CoW, while the back-end WoS is handed over to test and assembly houses to improve production efficiency and flexibility. 

However, the demand for advanced packaging capacity for AI chips still outstrips supply. Sources cited by CNA also reveal that NVIDIA has sought assistance from packaging and testing subcontractors outside of TSMC to augment their advanced packaging capabilities.

Amkor, among others, began gradually providing capacity support from the fourth quarter of last year, while SPIL, a subsidiary of ASE, is slated to commence supply in the first quarter of this year.

Read more

• [News] AMD Eyes CoWoS-like Supply for AI Chips with TSMC Full Capacity
• [News] CoWoS Capacity Shortage Challenges AI Chip Demand, while Taiwanese Manufacturers Expand to Seize Opportunities

(Photo credit: TSMC)

With the flourishing development of technologies such as AI, cloud computing, big data analytics, and mobile computing, modern society has an increasingly high demand for computing power.

Moreover, with the advancement beyond 3 nanometers, wafer sizes have encountered scaling limitations and manufacturing costs have increased. Therefore, besides continuing to develop advanced processes, the semiconductor industry is also exploring other ways to maintain chip size while ensuring high efficiency.

The concept of “heterogeneous integration” has become a contemporary focus, leading to the transition of chips from single-layer to advanced packaging with multiple layers stacked together.

The term “CoWoS” can be broken down into the following definitions: “Cow” stands for “Chip-on-Wafer,” referring to the stacking of chips, while “WoS” stands for “Wafer-on-Substrate,” which involves stacking chips on a substrate.

Therefore, “CoWoS” collectively refers to stacking chips and packaging them onto a substrate. This approach reduces the space required for chips and offers benefits in reducing power consumption and costs.

Among these, CoWoS can be further divided into 2.5D horizontal stacking (most famously exemplified by TSMC’s CoWoS) and 3D vertical stacking versions. In these configurations, various processor and memory modules are stacked layer by layer to create chiplets. Because its primary application lies in advanced processes, it is also referred to as advanced packaging.

According to TrendForce’s data, it has provided insights into the heat of the AI chip market. In 2023, shipments of AI servers (including those equipped with GPU, FPGA, ASIC, etc.) reached nearly 1.2 million units, a 38.4% increase from 2022, accounting for nearly 9% of the overall server shipments.

Looking ahead to 2026, the proportion is expected to reach 15%, with a compound annual growth rate (CAGR) of AI server shipments from 2022 to 2026 reaching 22%.

Due to the advanced packaging requirements of AI chips, TSMC’s 2.5D advanced packaging CoWoS technology is currently the primary technology used for AI chips.

GPUs, in particular, utilize higher specifications of HBM, which require the integration of core dies using 2.5D advanced packaging technology. The initial stage of chip stacking in CoWoS packaging, known as Chip on Wafer (CoW), primarily undergoes manufacturing at the fab using a 65-nanometer process. Following this, through-silicon via (TSV) is carried out, and the finalized products are stacked and packaged onto the substrate, known as Wafer on Substrate (WoS).

As a result, the production capacity of CoWoS packaging technology has become a significant bottleneck in AI chip output over the past year, and it remains a key factor in whether AI chip demand can be met in 2024. Foreign analysts have previously pointed out that NVIDIA is currently the largest customer of TSMC’s 2.5D advanced packaging CoWoS technology.

This includes NVIDIA’s H100 GPU, which utilizes TSMC’s 4-nanometer advanced process, as well as the A100 GPU, which uses TSMC’s 7-nanometer process, both of which are packaged using CoWoS technology. As a result, NVIDIA’s chips account for 40% to 50% of TSMC’s CoWoS packaging capacity. This is also why the high demand for NVIDIA chips has led to tight capacity for TSMC’s CoWoS packaging.

TSMC’s Expansion Plans Expected to Ease Tight Supply Situation in 2024

During the earnings call held in July 2023, TSMC announced its plans to double the CoWoS capacity, indicating that the supply-demand imbalance in the market could be alleviated by the end of 2024.

Subsequently, in late July 2023, TSMC announced an investment of nearly NTD 90 billion (roughly USD 2.87 billion) to establish an advanced packaging fab in the Tongluo Science Park, with the construction expected to be completed by the end of 2026 and mass production scheduled for the second or third quarter of 2027.

In addition, during the earnings call on January 18, 2024, TSMC’s CFO, Wendell Huang, emphasized that TSMC would continue its expansion of advanced processes in 2024. Therefore, it is estimated that 10% of the total capital expenditure for the year will be allocated towards expanding capacity in advanced packaging, testing, photomasks, and other areas.

In fact, NVIDIA’s CFO, Colette Kress, stated during an investor conference that the key process of CoWoS advanced packaging has been developed and certified with other suppliers. Kress further anticipated that supply would gradually increase over the coming quarters.

Regarding this, J.P. Morgan, an investment firm, pointed out that the bottleneck in CoWoS capacity is primarily due to the supply-demand gap in the interposer. This is because the TSV process is complex, and expanding capacity requires more high-precision equipment. However, the long lead time for high-precision equipment, coupled with the need for regular cleaning and inspection of existing equipment, has resulted in supply shortages.

Apart from TSMC’s dominance in the CoWoS advanced packaging market, other Taiwanese companies such as UMC, ASE Technology Holding, and Powertek Technology are also gradually entering the CoWoS advanced packaging market.

Among them, UMC expressed during an investor conference in late July 2023 that it is accelerating the deployment of silicon interposer technology and capacity to meet customer needs in the 2.5D advanced packaging sector.

UMC Expands Interposer Capacity; ASE Pushes Forward with VIPack Advanced Packaging Platform

UMC emphasizes that it is the world’s first foundry to offer an open system solution for silicon interposer manufacturing. Through this open system collaboration (UMC+OSAT), UMC can provide a fully validated supply chain for rapid mass production implementation.

On the other hand, in terms of shipment volume, ASE Group currently holds approximately a 32% market share in the global Outsourced Semiconductor Assembly and Test (OSAT) industry and accounts for over 50% of the OSAT shipment volume in Taiwan. Its subsidiary, ASE Semiconductor, also notes the recent focus on CoWoS packaging technology. ASE Group has been strategically positioning itself in advanced packaging, working closely with TSMC as a key partner.

ASE underscores the significance of its VIPack advanced packaging platform, designed to provide vertical interconnect integration solutions. VIPack represents the next generation of 3D heterogeneous integration architecture.

Leveraging advanced redistribution layer (RDL) processes, embedded integration, and 2.5D/3D packaging technologies, VIPack enables customers to integrate multiple chips into a single package, unlocking unprecedented innovation in various applications.

Powertech Technology Seeks Collaboration with Foundries; Winbond Electronics Offers Heterogeneous Integration Packaging Technology

In addition, the OSAT player Powertech Technology is actively expanding its presence in advanced packaging for logic chips and AI applications.

The collaboration between Powertech and Winbond is expected to offer customers various options for CoWoS advanced packaging, indicating that CoWoS-related advanced packaging products could be available as early as the second half of 2024.

Winbond Electronics emphasizes that the collaboration project will involve Winbond Electronics providing CUBE (Customized Ultra-High Bandwidth Element) DRAM, as well as customized silicon interposers and integrated decoupling capacitors, among other advanced technologies. These will be complemented by Powertech Technology’s 2.5D and 3D packaging services.

Read more

• [News] AMD Eyes CoWoS-like Supply for AI Chips with TSMC Full Capacity
• [News] Samsung Boosts 2.5D Packaging Equipment to Compete for TSMC’s CoWoS Orders

(Photo credit: TSMC)

Industry sources cited by the Liberty Times Net have pointed out that the Kumamoto plant holds significant importance for both Taiwan and Japan, as Japan is expected to look for attracting investments from TSMC, Intel, and Samsung to establish manufacturing facilities in the country.

TSMC stands out as essential due to its critical role as a key supplier to Apple, whose products are also utilized by the US military. Under geopolitical considerations, Apple needs to diversify its production beyond Taiwan and China. Therefore, it may hope TSMC can provide chip production in Japan soon and establish comprehensive advanced packaging services in the future. It seems inevitable that TSMC will eventually invest in setting up advanced packaging facilities in Japan.

Establishing Comprehensive Advanced Packaging Services

The TSMC Kumamoto plant commenced construction in April 2022 and was completed in just one year and eight months. While the construction of the US plant began in early 2021, setbacks in construction has led to the postponement of the production schedule from this year to the next.

Japan is also facing severe labor shortages, but the construction industry in Japan has made significant progress. It is highly industrialized, utilizing modular structures prefabricated in plants and then transported to construction sites for installation, thus reducing the need for on-site labor. In the construction of the Kumamoto plant, Japan’s construction firm, Kajima Corporation, was the general contractor.

German Construction Firm Sends Team to Learn from Japan

The German government actively subsidizes efforts to attract TSMC to invest in establishing  plants. In August last year, TSMC finalized partnerships with Bosch, Infineon, and NXP Semiconductors to form the European Semiconductor Manufacturing Company (ESMC) in Dresden, Germany.

According to a report from Liberty Times Net, construction is expected to begin in the second half of this year, with mass production slated to start by the end of 2027. It is also reported that Exyte, a German engineering services firm (formerly known as M+W), has recently sent a team to learn from the Kumamoto plant.

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(Photo credit: TSMC)

The latest financial reports for 4Q23 from six leading global semiconductor foundries signal optimism for the semiconductor industry’s recovery in 2024.

In 2023, the semiconductor sector underwent significant adjustments. As the industry worked towards normalizing its inventory levels amidst ongoing high inflation risks, the short-term market outlook remained unclear. #TrendForce has analyzed the latest financials from these six foundries to provide insights into what 2024 might hold for the industry.

TSMC

TSMC reported a slight YoY revenue decrease of 1.5% to US$19.62 billion in 4Q23, though it saw a 13.6% increase from the previous quarter. With an anticipated CAGR of 15–20%, TSMC’s 2024 capital expenditures are expected to be between $28 billion and $32 billion.

The company forecasts more than 10% growth in the semiconductor market (excluding memory) and around 20% growth in the wafer fabrication sector for 2024.

Samsung Electronics

Samsung Electronics’ 4Q23 consolidated revenue fell 3.81% YoY to ₩67.78 trillion. Its DS division reported revenues of ₩21.69 trillion but faced an operating loss of ₩2.18 trillion.

Despite the challenges, Samsung is focusing on advancing 3nm and 2nm GAA process technologies, expecting a revival in smartphone and PC demand in 2024 to rejuvenate the foundry market to its former prosperity.

Intel

Intel’s 4Q23 earnings saw a 10% revenue increase to $15.406 billion, with its foundry business, Intel Foundry Services, jumping 63% to $291 million in revenue.

Despite seasonal demand slumps in its core PC and server segments, Intel’s AI chips have accumulated $2 billion in orders, with sales forecast to improve in the second half of the year.

Global Foundries

GlobalFoundries reported a 12% revenue drop in 4Q23 to $1.85 billion, with a net income of $356 million. The company anticipates 1Q24 revenues to range between $1.5 billion and $1.54 billion, primarily due to the current industry-wide chip inventory adjustments.

Nevertheless, GlobalFoundries expects its 2023 automotive market revenue to surpass $1 billion, forecasting continued growth into 2024.

UMC

UMC disclosed a 19% YoY decrease in 4Q23 revenues to $1.79 billion. The company cited an extended semiconductor industry inventory adjustment period due to a challenging global economic climate, leading to a slight reduction in wafer shipments and capacity utilization. UMC expects a gradual uptick in wafer demand through 1Q24.

SMIC

SMIC reported a modest increase in 4Q23 revenues to $1.68 billion, with a 0-2% growth projection for 1Q24. Despite last year’s cyclical lows and competitive pressures, SMIC anticipates its 2024 revenue growth will at least match the industry average, with capital expenditures mirroring those of 2023.

TrendForce had earlier forecasted a delayed recovery in the end-market by the fourth quarter of 2023. However, they noted that inventory stocking by Chinese Android firms for the year-end sales rush—particularly for mid-to-low-end 5G and 4G smartphone application processors—alongside the influence of new Apple iPhone releases, might surpass initial expectations.

This indicates that the revenues of the world’s top ten semiconductor foundries are poised for growth, potentially surpassing the growth rates observed in the third quarter.

(Photo credit: Samsung)