In a bid to enhance its foundry capabilities, Samsung is earnestly integrating hybrid bonding technology. According to industry sources, Applied Materials and Besi Semiconductor are establishing equipment for hybrid bonding at the Cheonan Campus, slated for use in next-generation packaging solutions like X-Cube and SAINT.

According to a report from South Korean media outlet The Elec, industry sources have indicated that Applied Materials and Besi Semiconductor are installing hybrid bonding equipment at Samsung’s Cheonan Campus, a key site for advanced packaging production. Officials from the South Korean industry also mentioned that a production line is currently under construction, with the equipment intended for non-memory packaging.

Compared to existing bonding methods, hybrid bonding enhances I/O and wiring lengths. Samsung’s latest investment is expected to strengthen its advanced packaging capabilities, introducing the X-Cube utilizing hybrid bonding technology.

Industry sources cited by the report have suggested that hybrid bonding could also be applied to Samsung’s SAINT (Samsung Advanced Interconnect Technology) platform, which the company began introducing this year. The platform includes three types of 3D stacking technologies: SAINT S, SAINT L, and SAINT D.

SAINT S involves vertically stacking SRAM on logic chips such as CPUs. SAINT L involves stacking logic chips on top of other logic chips or application processors (APs). SAINT D entails vertical stacking of DRAM with logic chips like CPUs and GPUs.

TSMC, the leading semiconductor foundry, also offers hybrid bonding in its System on Integrated Chip (SoIC) for 3D packaging services, which is similarly provided by Applied Materials and Besi Semiconductor. Intel has also applied hybrid bonding technology in its 3D packaging technology, Foveros Direct, which was commercialized last year.

Reportedly, industry sources anticipate that Samsung’s investment in hybrid bonding facilities is poised to attract major clients such as NVIDIA and AMD. This is because the demand for hybrid bonding among fabless customers is steadily increasing.

(Photo credit: Samsung)

The competition for dominance in 2nm semiconductor technology has intensified at the beginning of 2024, marking a crucial battleground among global foundry companies.

As per a report from IJIWEI, major foundry enterprises such as Samsung Electronics, TSMC, and Intel are set to commence mass production adopting 2nm process starting this year. Consequently, the fierce competition for supremacy in 2nm technology is expected to escalate from 2025 onwards. Currently, the most advanced production technology globally is at the 3nm level.

• TSMC

TSMC’s 2nm products will be manufactured at the Fab 20 in the Hsinchu Science Park in northern Taiwan and at a plant in Kaohsiung.

The Fab 20 facility is expected to begin receiving related equipment for 2nm production as early as April, with plans to transition to GAA (Gate-All-Around) technology from FinFET for 2nm mass production by 2025.

During TSMC’s earnings call on January 18th, TSMC revealed that its capital expenditure for this year is expected to fall between USD 28 billion and 32 billion, with the majority (70% to 80%) allocated to advanced processes. This figure is similar to that of 2023 (USD 30.4 billion), indicating stable investment to ensure its leading position in 2nm technology.

• Intel

After announcing its re-entry into the foundry business, Intel is actively advancing its foundry construction efforts. The plan includes the introduction of the Intel 20A (equivalent to 2nm) process in the first half of 2024 and the Intel 18A (1.8nm) process in the second half of the year. It is understood that the Intel 18A process will commence test production as early as the first quarter of this year.

Intel’s 2nm roadmap is more ambitious than originally anticipated, being accelerated by over six months. In response to criticisms of its “overly ambitious” plans, Intel swiftly began procuring advanced Extreme Ultraviolet (EUV) equipment.

• Samsung Electronics

Samsung Electronics has devised a strategy to gain an advantage in the more advanced process war through its Gate-All-Around (GAA) technology. Currently, it is mass-producing the first-generation 3nm process based on GAA (SF3E) and plans to commence mass production of the second-generation 3nm process this year, significantly enhancing performance and power efficiency.

Regarding the 2nm process, per a report from Nikkei, Samsung plans to start mass production for mobile devices in 2025 (SF2) and gradually expand to high-performance computing (HPC) in 2026 and automotive processes in 2027.

Currently, Samsung Electronics is producing GAA products for the 3nm process at its Hwaseong plant and plans to manufacture products for both the 3nm and 2nm processes at its Pyeongtaek facility in the future.

• Rapidus

Rapidus, a chip manufacturing company supported by the Japanese government, is expected to trial-adopt 2nm process at its new plant by 2025 and begin mass production from 2027.

If Rapidus’ technology is validated, the global foundry market may expand beyond the Taiwan-Korea duopoly to include Taiwan, Korea, the United States, and Japan.

The technology competition to become a “game-changer” ultimately depends on the competition for customers. It’s rumored that TSMC holds a leading position in the 2nm field, with Apple speculated to be its first customer for the 2nm process. Graphics processing giant NVIDIA is also considered a major customer within TSMC’s client base.

According to TrendForce data as of the third quarter of 2023, TSMC’s revenue share accounted for a dominant 57.9%, with Samsung Electronics trailing at 12.4%, a gap of 45.5 percentage points.

However, Samsung Electronics is not sitting idly by. With continuous technological investment, Samsung’s foundry customer base grew to over 100 in 2022, a 2.4-fold increase from 2017. The company aims to expand this number to around 200 by 2028.

Particularly, Samsung’s early adoption of GAA technology is expected to give it an advantage in achieving early production volumes for advanced processes.

Read more

• Top 10 Foundries Experience 7.9% QoQ Growth in 3Q23, with a Continued Upward Trend Predicted for Q4, Says TrendForce
• [News] Intense Competition with Samsung and Intel in Advanced Processes; TSMC Speeds Up 2nm Progress

(Photo credit: TSMC)

NVIDIA’s AI chip supply faces constraints, with insufficient CoWoS advanced packaging production capacity at TSMC potentially being the main issue. According to Economic Daily News, NVIDIA is also providing advanced packaging services to Intel, with a monthly capacity of about 5,000 units. It is expected to join NVIDIA’s advanced packaging supply chain as early as the second quarter in 2024, grabbing a share of TSMC’s related orders.

Industry sources cited by the Economic Daily News believe that Intel’s participation will help alleviate the tight supply of AI chips.

TSMC declined to comment on the rumors on January 30th. As per industry sources cited by Economic Daily News, Intel’s entry into NVIDIA’s advanced packaging supply chain is expected to lead to a significant increase of nearly ten percent in total production capacity.

As per industry analysis cited in the report, even with Intel joining to provide advanced packaging capacity for NVIDIA, TSMC remains NVIDIA’s primary supplier for advanced packaging. When considering the expanded production capacity of TSMC and other related assembly and testing partners, it is estimated that they will supply approximately 90% of advanced packaging capacity for NVIDIA.

Supply chain sources cited by the report further indicate that TSMC is ramping up its advanced packaging production capacity. Production capacity is estimated to increase to nearly 50,000 units in the first quarter of this year, representing a 25% increase from the estimated nearly 40,000 units in December last year.

While Intel may potentially provide NVIDIA with nearly 5,000 units of advanced packaging capacity, this accounts for about 10% of the total. However, Intel is reportedly not involved in NVIDIA’s AI chip foundry orders.

Intel has advanced packaging capacity in Oregon and New Mexico in the United States and is actively expanding its advanced packaging capabilities in its new facility in Penang. It is noteworthy that Intel previously stated its intention to offer customers the option to only use its advanced packaging solutions, expected to provide customers with greater production flexibility.

Industry sources also indicate that the previous shortage of AI chips stemmed from three main factors: insufficient capacity in advanced packaging, tight supply of high-bandwidth memory (HBM3), and some cloud service providers placing duplicate orders. However, these bottlenecks have gradually been resolved, and the improvement rate is better than expected.

(Photo credit: Intel)

Read more

• [News] Intense Competition with Samsung and Intel in Advanced Processes; TSMC Speeds Up 2nm Progress

With the highly anticipated opening of TSMC’s Kumamoto fab on February 24th, 2024, multiple Japanese or global semiconductor manufacturers are set to begin large-scale production in newly established plants in Japan.

According to sources cited by TechNews, this development will stimulate the growth and advancement of Japan’s domestic semiconductor supply chain, enhancing Japan’s semiconductor manufacturing capabilities, transitioning from Renesas Electronics’ 40-nanometer process to JASM’s 12-nanometer process.

TSMC Kumamoto Fab Set to Open on February 24

In Kikuyo Town, Kumamoto Prefecture, Japan Advanced Semiconductor Manufacturing (JASM) company, jointly invested by TSMC, SONY, and Japan’s DENSO, is currently constructing a 12-inch fab.

▲ TSMC’s Layout of Global Production Capacity Edited by TrendForce, January, 2024

The facility will employ 12/16-nanometer and 22/28-nanometer process, focusing on the production of chips for automotive electronic applications. The fab is scheduled to open on February 24, with mass production expected to commence in the fourth quarter of 2024.

This shift is regarded as the first step in Japan’s semiconductor revitalization policy. In support of this initiative, the Japanese government has provided a financial subsidy of JPY 476 billion (approximately USD 3.2 billion) to the JASM fab, covering nearly one-third of the total expenditure, which amounts to USD 8.6 billion.

Kioxia and Western Digital Jointly Constructing 12-Inch Plant

NAND Flash memory giants Kioxia and Western Digital are jointly investing in the construction of a 12-inch plant in Yokkaichi, Mie Prefecture. The facility is set to begin preparing for mass production of 3D NAND Flash memory products by March 2024.

Industry sources note that the plant’s construction will cost JPY 280 billion (approximately USD 1.8 billion ), with the Japanese government providing up to 92.9 billion yen (approximately USD 600 million) in subsidies.

Another Kioxia and Western Digital joint venture plant located in Kitakami, Iwate Prefecture, is slated to open in the second half of 2024. Originally scheduled for completion in 2023, the project faced delays due to unfavorable market conditions.

Renesas Electronics Expands Power Semiconductor Capacity

Renesas Electronics is set to launch a new power semiconductor production line in 2024. However, since the company’s Kofu factory in Yamanashi Prefecture closed in October 2014, Renesas is committing JPY 90 billion to install a 12-inch wafer production line at its existing facility to meet the growing demand for power semiconductors, especially in electric vehicles (EVs).

The new production line will enable Renesas Electronics to enhance its capacity for power semiconductors such as IGBT and MOSFET, with plans to achieve mass production by 2024. Renesas Electronics’ expansion plan is expected to receive subsidy support from the Japanese Ministry of Economy, Trade, and Industry.

Toshiba and ROHM Semiconductor Collaborate to Integrate Production Lines for Power Semiconductors

Toshiba and ROHM Semiconductor have reached an agreement to collaborate. Under the agreement, Toshiba’s power semiconductor factory will begin integrating production with ROHM’s newly developed Silicon Carbide (SiC) power semiconductor plant in Kunitomi City, Miyazaki Prefecture. This collaboration is expected to receive government subsidies equivalent to one-third of the investment in the project.

Japan’s New Fab Projects Beyond 2025

Beyond 2025, Japan is set to witness the emergence of several new plants, including Micron Technology’s new 1-gamma (1γ) DRAM production facility in Hiroshima Prefecture.

JSMC, a foundry subsidiary of Powerchip Semiconductor Manufacturing Corporation (PSMC), is collaborating with Japan’s financial group SBI to complete construction by 2027 and begin chip production thereafter.

Additionally, Japanese semiconductor startup Rapidus plans to commence production of 2-nanometer chips in Hokkaido by 2027.

Furthermore, TSMC is currently evaluating plans for its second plant in Japan, expected to be located in Kikuyo Town, Kumamoto Prefecture. Reports suggest that TSMC is set to officially announce the location of the second wafer plant on February 6th.

Earlier discussions by TSMC Chairman Mark Liu regarding the second plant in Japan indicated ongoing evaluations and discussions with the Japanese government. Once the decision to build the second plant is finalized, it is anticipated to manufacture products utilizing 7-nanometer to 16-nanometer process technologies.

Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

However, the looming shortage of semiconductor talent in Japan is a concern. In response, there are generous subsidy programs for talent development. Japan is strategically positioning itself to reclaim its former glory in the world of semiconductors.

Read more

• [News] TSMC Reportedly Announcing Kumamoto Plant 2 in Japan, while U.S. Subsidies Expected by End of March
• [News] ROHM Eyes R&D Expansion in Power Semiconductor Production Venture with Toshiba

(Photo credit: TSMC)

While TSMC is pushing forward with its 2nm fab in Taiwan, there is also good news about its overseas expansion. According to the Japanese newspaper “Kumanichi,” TSMC is expected to announce the construction of its Kumamoto Fab 2 in Japan on February 6, with the possibility of incorporating the 7nm process. Additionally, the United States is also expected to provide several billion dollars in subsidies to TSMC’s new fab by the end of March.

▲ TSMC’s Layout of Global Production Capacity Edited by TrendForce, January, 2024

Per the report from the ” Kumanichi,” Japan’s Minister of Agriculture, Forestry, and Fisheries, Tetsushi Sakamoto, who hails from Kumamoto, stated during a local meeting on January 28th that TSMC is evaluating Kumamoto Prefecture’s Kikuyo Town as the location for its second fab. The announcement of the site for Fab 2 in Kumamoto is expected to be made as early as February 6th.

The report further indicates that Fab 2 is expected to be situated next to the first fab, which was completed at the end of last year. TSMC had previously mentioned that if a second fab were to be constructed, it would be located in the vicinity of the existing facility under construction.

Regarding the rumors, the spokesperson for TSMC stated that the expansion strategy of TSMC’s global manufacturing footprint is based on considerations of customer demand, business opportunities, operational efficiency, government support, and economic costs.

Through necessary investments, TSMC continues to support customer demands and respond to the structural growth of semiconductor technology in the long term. “We are currently focusing on evaluating the possibility of setting up a second fab in Japan, and there is no further information to share at the moment.”

During the recent earnings call, Mark Liu also mentioned that the plan for TSMC’s second fab in Japan is still under evaluation. However, he hinted at the possibility of adopting the 7-nanometer process.

TSMC’s Kumamoto plant is scheduled to hold its opening ceremony on February 24th. After retiring following the shareholders’ meeting in June this year, TSMC Chairman Mark Liu, along with the designated successor and current President C.C.Wei, will lead several top executives to Japan for the event. TSMC has also invited Japanese Prime Minister Fumio Kishida to attend.

The decision for TSMC to establish a plant in Kumamoto, Japan, was announced in October 2021, and construction began in 2022. In comparison to TSMC’s announcement of a plant in the United States in 2020, which faced delays and is set to commence production in 2025, the Japanese plant has advanced more swiftly.

This aligns with TSMC founder Morris Chang’s statement last year that Japan is considered an ideal location for establishing a semiconductor supply chain.

Analyst Joanne Chiao from TrendForce previously pointed out that Japan’s expertise in materials and machinery is one of the factors attracting TSMC’s expansion. Japan stands to benefit from TSMC’s establishment as the pace of creating a local semiconductor ecosystem by Japanese government surpasses that of the U.S. government.

On the other hand, despite TSMC delaying the production at its new US plant, according to Bloomberg, the United States plans to announce substantial chip subsidies by the end of March. The aim is to pave the way for chip manufacturers like TSMC and Intel by providing them with billions of dollars to accelerate the expansion of domestic chip production.

These subsidies are a core component of the US 2022 “CHIPS and Science Act,” which allocates a budget of USD 39 billion to directly subsidize and revitalize American manufacturing.

Read more

• [News] Completion of TSMC’s Kumamoto Plant, Grand Opening on 2/24
• [News] Rumored to Build Third Plant in Kumamoto, TSMC: Currently Focusing on Assessing the Construction of a Second Plant

(Photo credit: TSMC)