Amidst geopolitical influences, governments worldwide are enticing semiconductor manufacturers with subsidy policies, prompting chip manufactures to establish themselves in various regions. The ongoing dynamics of semiconductor facility construction and the evolving global production capacity remain focal points for the industry in 2024.

Following TSMC’s establishment of facilities in Arizona, USA, and Kumamoto, Japan, the progress of TSMC’s second Kumamoto plant has garnered significant industry attention. On another front, the developments at TSMC’s ESMC facility in Germany continue to capture global attention within the semiconductor industry.

Powerchip Semiconductor Corporation (PSMC) also made headlines in 2023 by announcing the construction of its first overseas 12-inch fab, JSMC, located in Sendai City, Miyagi Prefecture, Japan.

Meanwhile, Samsung’s overseas expansion efforts are equally robust. In addition to its Taylor plant in the United States, Samsung plans to establish a new semiconductor packaging research center in Japan.

According to TrendForce data, considering an equivalent foundry capacity of 12 inches, Taiwan held a global market share of approximately 47% in 2023, followed by China at 26%, South Korea at 12%, the United States at 6%, Singapore at 4%, Japan at 2%, Germany at 1%, and others at 2%. By 2027, Taiwan’s market share is projected to decrease to 42%, with China at 28%, South Korea at 10%, the United States at 7%, Singapore at 6%, Japan at 3%, Germany at 2%, and others at 1%.

(Image: TSMC)

With the successful mass production of TSMC’s 3nm process and preparations for the upcoming 2nm process, recent reports suggest that TSMC has awarded a special contribution bonus to its research and development team in December, acknowledging the hard work of its employees.

In response to the news about the special contribution bonuses in December, TSMC stated that the company has always upheld the belief that “employees are the company’s most important assets” and this move is part of the ongoing commitment to taking care of its workforce.

According to reports citing from the industry sources, TSMC successfully commenced production of 3nm chips last year, and mass production is on track for the latter half of this year. Following this, advancements are being made in advanced processes, including 2nm and the development of processes such as A14 (1.4nm) and A10.

Specifically, after smooth research and development trials of the 2nm process this year, it will be integrated into the completed construction of Fab 20 in Baoshan, Hsinchu. The team at this facility is gearing up for risk production in 2024 and aims for mass production in 2025. A14 is expected to undergo trial production and mass production between 2027 and 2028.

TSMC has previously mentioned in its Earning Conference that the 2nm process technology will adopt a Nanosheet transistor structure, enhancing performance to meet the growing demand for energy-efficient computing.

Additionally, the 2nm family has developed backside power rail solution, particularly suitable for high-speed computing applications. The goal is to launch this solution for customer adoption in the latter half of 2025 and begin mass production in 2026.

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(Photo credit: TSMC)

As competition in the semiconductor industry intensifies, countries worldwide are implementing industrial policies to attract domestic and foreign investments. Japan, in particular, has introduced substantial subsidies to entice industry players to invest and establish facilities.

According to the report from South Korean “Dong-a Ilbo,” compared to other nations, South Korea’s semiconductor industry lacks sufficient subsidies, and there are concerns that Japan may surpass South Korea within the next decade.

Given the high cost of advanced semiconductor facility equipment and relatively higher local labor and other costs in Japan compared to other Asian countries, semiconductor companies are making substantial investments, often in the trillions of yen, to set up facilities in Japan.

In an effort to attract foreign companies to establish facilities in Japan, the Japanese government not only promotes the capabilities of numerous domestic semiconductor upstream suppliers to meet supply chain demands but also provides subsidies to alleviate the burden on industry players, thereby enhancing the competitiveness of products manufactured in Japan.

Taking memory giant Micron as an example, reportedly, Micron’s DRAM plant being constructed in Hiroshima, Japan, has received a 39% subsidy from the Japanese government for the construction cost. This subsidy has enhanced its cost competitiveness by 5% to 7%.

With substantial assistance from the Japanese government, there is a potential for Micron to narrow the market share gap with Samsung Electronics and SK Hynix in the future.

In recent years, TSMC has also chosen to establish a plant in Kumamoto, Japan, under the active solicitation of the Japanese government. In June of the previous year, the Japanese Ministry of Economy, Trade, and Industry announced that TSMC, along with Sony and Denso, jointly investing in Kumamoto Fab 1, could receive a maximum subsidy of JPY 476 billion (approximately USD 3.34 billion), equivalent to half of the construction cost.

The head of the Japanese Semiconductor Strategic Promotion Council, Akira Amari, previously mentioned that the Japanese government would provide one-third of the construction cost as a subsidy for TSMC’s Kumamoto Fab 2.

However, in November of this year, the Japanese Cabinet approved a semiconductor subsidy plan of nearly JPY 2 trillion, deciding to grant a subsidy of JPY 900 billion to TSMC’s Kumamoto Fab 2, exceeding one-third of the construction cost.

As per TrendForce’s report, Japan is also actively supporting local company Rapidus with a goal of reaching the most advanced 2 nm process. They aim to create a semiconductor cluster in Hokkaido and are offering subsidies to foreign companies, including Japan Advanced Semiconductor Manufacturing (JASM) and PSMC’s Sendai plant (JSMC).

This dual-pronged approach by the Japanese government aims to attract both domestic and foreign semiconductor industry investments in Japan.

While the South Korean parliament expanded tax incentives for semiconductor facility investment in the chip law passed in March of this year, it did not provide direct cash subsidies, raising concerns among industry professionals about the potential overtaking of the South Korean semiconductor industry by Japan.

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(Photo credit: TSMC)

TSMC’s 2nm fab, strategically positioned between the Hsinchu Science Park and the Nanzih Technology Industrial Park in Kaohsiung Science Park, is rapidly taking shape.

According to Liberty Times Net, reports from the supply chain suggest that up to five fabs could be constructed in the Nanzih. The first of these fabs, currently under construction, is scheduled to begin its tool-in in January 2025.

Furthermore, there are indications that construction for the second fab may commence in the near future. There is also speculation that the third fab might be designated for the production of 2nm process, although this possibility has not been ruled out.

Chen Chi-Mai, Mayor of Kaohsiung city, mentioned that the progress of the first fab is proceeding as scheduled as expectations. Additionally, miscellaneous permits for the second fab were issued to TSMC in mid-December, 2023

While the semiconductor industry is still undergoing inventory adjustments, TSMC still continues its pursuit of advanced process over Intel and Samsung. Construction is underway for the new 2nm fab, with the steel structure completed for the Baoshan 2nm fab in the Hsinchu Science Park, including the cleanroom, is currently in progress.

According to Wayne Wang, the director-general of the Hsinchu Science Park Bureau, Baoshan Phase 2 will serve as one of TSMC’s production bases for 2nm process. Simultaneously, public construction projects and fab construction are proceeding, with the first plant set to tool-in in April next year, following the completion of workflow inspections.

Nanzih is also a primary production base for TSMC’s 2nm fab. The initial plan for the first fab was to produce chips using the 28nm and 7nm process. However, in response to geopolitical and economic changes, the decision was made to switch to the 2nm process.

Due to the different specifications on each semiconductor equipment, the Nanzih project began earlier this year, and faced challenges. However, the design was subsequently modified right off the bat, and re-started. For now, the progress is halfway through the whole project.

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(Photo credit: TSMC)

TSMC, the world’s leading foundry in the 3nm technology, is reportedly experiencing a surge in the number of New Tape-Outs (NTOs) for the 3nm family in 2024, with Clients such as MediaTek, AMD, NVIDIA, Qualcomm, and Intel.

Among the 3nm family, the N3P process, set for mass production in the second half of 2024, is also making significant progress. Rumors suggest that Tesla has been added to the list of customers, with plans to utilize the N3P for the production of next-generation Full Self-Driving (FSD) chips after its launch.

Currently, Tesla has placed orders with TSMC for numerous chips related to electric vehicles. For instance, the supercomputer chip “D1” is utilizing TSMC’s 7nm technology along with advanced packaging processes.

Reportedly, according to industry sources, Tesla’s older FSD chips were initially produced using Samsung’s 14nm process, later upgraded to Samsung’s 7nm process. Subsequently, considering design upgrades, production quality, and scale, Tesla has shifted its HW 4.0 autonomous driving chip production to TSMC, utilizing the 5nm technology family.

The latest information per the report indicates that Tesla has recently initiated a NTO process with TSMC, planning to utilize the N3P for the production of the fifth generation of self-driving vehicle chips. Market expectations are high, with the influx of relevant orders suggesting that Tesla has the potential to become one of TSMC’s major clients.

According to TSMC’s previously disclosed process roadmap, the N3P process is an advanced version within the 3nm family, scheduled for production in 2024. Compared to the N3E, the N3P boasts a 5% improvement in performance, a 5% to 10% reduction in power consumption, and a 1.04 times increase in chip density.

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(Photo credit: TSMC)