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In a bid to revitalize its semiconductor industry, Japan has enticed the sector with subsidies worth trillions of yen, aiming to attract both domestic and international semiconductor companies.
Leading semiconductor foundry Taiwan Semiconductor Manufacturing Co. (TSMC) has invested USD 8.6 billion to construct a factory in Kumamoto Plant, and it is considering building a second plant nearby. According to reports, TSMC is also contemplating a third plant within Kumamoto Prefecture to produce cutting-edge 3nm chips.
Apart from TSMC, major players like Samsung and Powerchip Semiconductor Manufacturing Corporation (PSMC) are actively investing in Japan. The initiatives of these giants have not only influenced semiconductor manufacturing equipment suppliers in Japan but also spurred them to accelerate technological research and expand production capacity.
As a result of these efforts, the investment of Japan’s six major semiconductor equipment suppliers has surged by 70% over the past five years.
TSMC Kumamoto New Plant Aims for Monthly Production of 55,000 12-Inch Wafers
Reportedly, the new chip plant in Kumamoto, Japan, operated by Japan Advanced Semiconductor Manufacturing (JASM), a joint venture between TSMC, Sony, and Denso, is poised for commencing production in the fourth quarter of 2024, while the plant’s production capacity will target a full capacity of 55,000 12-inch wafers per month.
Simultaneously, JASM aims to enhance the local contribution of semiconductor supply chain and ecosystem in Japan from the current 25% to 60% by 2030.
Meanwhile, according to sources cited by Bloomberg, TSMC has informed its supply chain partners that it is considering building a third factory in Kumamoto Plant in southern Japan, codenamed TSMC Fab-23 Phase 3.
TrendForce’s analysis mentioned that Japan’s expertise in semiconductor materials and machinery makes it an attractive location for TSMC’s expansion.
Additionally, Japan’s critical role in semiconductors and raw materials, coupled with collaboration with Sony, provides TSMC with significant advantages. TSMC’s investment in Japan is expected to facilitate access to advanced materials and expertise in CIS technology.
Furthermore, industry speculation suggests that in the future, Japan will not only continue subsidizing semiconductor manufacturing but also enhance collaboration between the semiconductor industry and academia to attract more talent to join the semiconductor industry.
PSMC Japanese Plant Aims for Monthly Production of 40,000 12-Inch Wafers
In late October, PSMC, in collaboration with SBI Holdings, Inc., the Miyagi Prefecture of Japan, and JSMC Corporation, signed a memorandum of understanding. The memorandum confirmed that JSMC’s first semiconductor wafer plant is expected to be located in the Second Northern Sendai Central Industrial Park in Ohira Village, Kurokawa District, Miyagi Prefecture (Second Northern Sendai Central Industrial Park).
The plant will produce 28nm, 40nm, and 55nm chips for automotive and industrial applications, with a planned monthly production of 40,000 12-inch wafers. Previous reports indicated that PSMC plans to construct multiple plants, with the first phase potentially starting construction as early as 2024, involving an investment of around JPY 400 billion (USD 2.6 billion).
The Japanese Ministry of Economy, Trade, and Industry (METI) is expected to provide up to JPY 140 billion in subsidies for the project, targeting operational commencement by 2026. The timeline and plans for the second phase are yet to be determined, with a total investment of approximately JPY 800 billion.
Regarding subsidies, PSMC stated that once Japan announces the subsidy amount for this semiconductor wafer plant investment, all relevant parties will reconfirm the effectiveness of this memorandum of understanding and proceed with the planned construction.
Is Foundry Revenue Expected to Continue its Upward Trend?
In the semiconductor industry chain, the significance of the foundry industry is self-evident. In recent years, the foundry sector has been affected by headwinds in end markets such as consumer electronics. However, as entering the latter half of the year, there are gradually emerging positive signals in the semiconductor industry.
According to TrendForce’s report on December 6th, looking ahead to 4Q23, TrendForce’s anticipation of year-end festive demand is expected to sustain the inflow of urgent orders for smartphones and laptops, particularly for smartphone components.
Although the end-user market is yet to fully recover, pre-sales season stockpiling for Chinese Android smartphones appears to be slightly better than expected, with demand for mid-to-low range 5G and 4G phone APs and continued interest in new iPhone models. This scenario suggests a continued upward trend for the top ten global foundries in Q4, potentially exceeding the growth rate seen in Q3.
According to the Semiconductor Equipment and Materials International (SEMI) report presented at SEMICON Japan 2023 on December 12, the global semiconductor equipment market is anticipated to experience a 6.1% year-on-year decline to USD 100.9 billion in sales for new equipment in 2023, marking the first contraction in four years.
However, the forecast for 2024 shows a reversal, with the semiconductor equipment market expected to grow by 4%, reaching USD 105.3 billion in sales. In 2025, a substantial increase of 18% is projected, surpassing the historical high of USD 107.4 billion in 2022.
SEMI CEO Ajit Manocha has noted that the semiconductor market exhibits cyclical patterns, with a short-term downturn expected in 2023. However, he anticipates a turning point towards recovery in 2024.
The year 2025 is poised for robust recovery, driven by increased production capacity, the construction of new wafer fabs, and growing demand for advanced technologies and solutions.
Major Companies Indirectly Boost Chip Equipment Investment in Japan, Surging 70% in 5 Years
According to a report by Nikkei, the proactive investments by semiconductor giants such as TSMC and Micron in Japan have accelerated technological innovations and production capacity expansion among Japanese chip equipment manufacturers.
The combined investment (including R&D and equipment investment) of Japan’s six major chip equipment firms, namely TEL, DISCO, Advantest, Lasertec, Tokyo Seimitsu, and Screen Holdings, for the fiscal year 2023 (April 2023 – March 2024) is approximately JPY 547 billion, marking a significant 70% increase compared to the 2018 fiscal year.
On December 13, Tokyo Electron Limited (TEL) President Tony Kawai stated at SEMICON Japan 2023 that the semiconductor market is projected to exceed USD 1 trillion by 2030, highlighting the immense potential within the industry.
On December 14, Hisashi Kanazashi, the Duputy Director at METI of Japan, noted that top overseas semiconductor firms plan to collaborate with Japan’s strength in “equipment” and expand their research and development presence in Japan.
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(Photo credit: TSMC)
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While TSMC makes promising strides in the 2nm process, slated for mass production in 2025, rivals Samsung and Intel are making headlines with aggressive moves to secure cost-effective deals. This surge in competition for the 2nm process is intensifying.
According to CNA, experts suggest that given the escalating rivalry in the AI chip market, it is paramount to have flawless execution in the process. Despite the recent efforts from Samsung and Intel, TSMC is anticipated to clinch the lion’s share of 2nm orders.
TSMC’s 2nm process is on track for mass production in 2025, with construction underway at its first 2nm fab in the Phase 2 Expansion Area of the Baoshan Site in the Hsinchu Science Park. The tool-in is scheduled for April next year. Simultaneously, TSMC’s Kaohsiung fab is earmarked as a crucial production base for 2nm in the future.
Samsung is gearing up for mass production of its 2nm process in 2025 as well. Reports from the Financial Times indicate that, in a bid to secure orders from industry giants like NVIDIA, Samsung is contemplating discounted offerings to challenge TSMC.
Intel, in its bid to reclaim its place in the semiconductor landscape, has set an big target of advancing 5 nodes in four years. Sanjay Natarajan, Senior Vice President at Intel, revealed in a recent interview with Nikkei Asia that the company aims to commence mass production of 2nm chips in 2024, with a commitment to providing reasonably priced products. Additionally, Intel’s 18A process is poised for trial production in the first quarter of 2024.
Analysts also share the insights of the competitive landscape among the three major semiconductor players, TSMC, Samsung, and Intel. Arisa Liu, the research fellow and director at the Taiwan Industry Economics Services of Taiwan Institute of Economic Research, notes that TSMC’s 2nm is expected to adopt a gate-all-around (GAA) architecture. In contrast, Samsung has taken an early lead by introducing GAA architecture in its 3nm, aiming to outpace TSMC in the 2nm process after 1 or 2 years of adjustments.
Liu highlights the challenges facing Samsung, noting that the 3nm GAA process has exhibited unstable yields. For example, Qualcomm, a major player in mobile chip, has reverted to TSMC for production. Even with Samsung’s plans for bidding at a reduced price, it is anticipated to face difficulties in denting TSMC’s order share in the short term.
Turning attention to Intel, Liu observes that Intel’s current process technology has advanced to Intel 4 and Intel 3, which do not align with the industry’s 4nm and 3nm processes. In reality, Intel’s progress is closer to 7nm or an enhanced version thereof. Notably, Intel’s 3nm products are still estimated to be outsourced to TSMC, signaling a substantial technology gap.
TSMC’s President, C.C. Wei, has previously outlined the company’s plan to initiate mass production of the 3nm N3P process in the latter half of 2024. Notably, its performance metrics, including power, performance, area (PPA), are expected to surpass Intel’s 18A.
Liu further pointed out the news of TSMC’s clients contemplating additional foundry partners has surfaced recently. This move is primarily seen as an attempt to exert pressure on TSMC and gain negotiating leverage. Given the fierce competition in the AI chip market, it is imperative to control precision in the manufacturing process. As such, TSMC’s 2nm is anticipated to secure a significant majority of orders.
(Image: TSMC)
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In mid-December, Intel is set to unveil its latest Core Ultra processor, Meteor Lake. Global PC brands like Lenovo, Microsoft, DELL, HP, Acer, Asus, MSI, and Samsung are rolling out new products to capture the market. The end-users is enthusiastic, and channel feedback suggests increasing orders, marking a turning point in the PC industry, according to CTEE.
As per the designs by PC brands, AI PCs are poised to offer AI and machine learning, capable of executing intelligent applications and tasks at the edge. This translates to a boost in user productivity and entertainment experiences, enhanced communication efficiency, and improved work quality. Furthermore, these PCs prioritize data and privacy protection.
Taiwanese partners have corresponding models entering the market, with analysts anticipating AI PCs to become the primary driver for replacement demand in the latter half of the next year. Shipment volumes are estimated to surpass 100 million units in the next two years, benefiting Taiwan’s supply chain, including PC brands Acer, Asus, MSI, and ODMs Quanta, Compal, and Inventec.
On the other hand, TSMC stands up as a major upstream player, with rising utilization rate of the 5nm and 6nm advanced processes contributed to the big orders from the Meteor Lake. TSMC is in charge of the NPU, specifically designed for AI tasks.
Intel highlights 3D Foveros as the key to advanced packaging in mixing and matching compute tiles. This aspect is managed by its advanced packaging fab in Malaysia, ensuring the most efficient energy distribution.
(Image: Intel)
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The new chip plant in Kumamoto, Japan, operated by Japan Advanced Semiconductor Manufacturing (JASM), a joint venture between Taiwan Semiconductor Manufacturing Co. (TSMC), Sony, and Denso, is poised for substantial capacity growth.
JASM President Yuichi Horita revealed that after commencing production in the fourth quarter of 2024, the plant’s production capacity will gradually ramp up, targeting a full capacity of 55,000 12-inch wafers per month.
Simultaneously, TSMC aims to enhance Japan’s semiconductor supply chain and ecosystem, looking to a 60% local contribution by 2030, a significant increase from the current 25%.
Yuichi Horita unveiled the latest plan for TSMC’s Kumamoto plant during his speech at the SEMICON Japan. He emphasized that TSMC’s Kumamoto plant is actively working to establish a local supply chain and ecosystem in Japan.
The current proportion of equipment and materials sourced from Japan for the Kumamoto plant is approximately 25%. The goal is to increase this to 50% by 2026 and achieve 60% by 2030. The progress in constructing production capacity, trial production, and mass production is in line with the original plan.
Yuichi Horita stated that the current workforce at the Kumamoto facility stands at 1,700 employees. Among them, around 600 are dispatched by TSMC and Sony, with the remaining being newly recruited staff.
The production capacity of the new Kumamoto plant primarily focuses on 28/22 nanometers and 16/12 nanometers. In the initial phase, the majority of the capacity is allocated to the manufacturing of Image Signal Processor (ISP) used in CMOS image sensors, as part of Sony’s outsourcing.
The remaining capacity is dedicated to automotive parts supplier Denso, where they outsource the production of automotive microcontroller unit (MCU), with Denso reportedly able to obtain approximately 10,000 wafers per month.
Reportedly, in industry analysis, although Japan’s recent performance in foundry has not matched that of Taiwan, South Korea, and China, Japan’s semiconductor equipment supply chain is already quite mature and comprehensive.
Major players in the field, such as Nikon in lithography equipment, and Hitachi High-Tech, renowned for etching equipment and critical dimension scanning electron microscopy (CD-SEM), have established dominance.
Additionally, Japanese companies specializing in chemical solutions, gases, and materials have also secured significant positions. All of these factors make them crucial partners for supporting the development of TSMC’s Kumamoto plant in the future.
Industry source suggests that in the future, the Japanese government will not only continue to subsidize semiconductor manufacturing but also strengthen collaboration between the semiconductor industry and academia to attract more talent into the semiconductor industry.
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(Photo credit: TSMC)
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Despite the uncertainties in the semiconductor market, there is still an intense global competition in the development of advanced semiconductor manufacturing processes. TSMC as one of the key players in the foundry industry is actively advancing its next-generation 2nm process. According to market rumors, the schedule for the first tool-in at Hsinchu Baoshan Fab and Kaohsiung Fab has been established, along with a finalized production capacity plan.
CNA has reported that TSMC’s 2nm process will be deployed in the Phase 2 Expansion Area of the Baoshan Site at the Hsinchu Science Park. The first tool-in is scheduled for April 2024. Industry sources have revealed that the initial production capacity for this process will be around 30,000 wafers per month, with mass production planned for the following year.
In addition, TSMC’s fab in Kaohsiung has notified equipment suppliers that this facility is set to begin in the third quarter of 2025. According to MoneyDJ, the pilot run is planned for the end of the same year, with the aim of achieving mass production in 2026. The Kaohsiung fab will adopt the N2P process, which is an enhanced version of the 2nm process with the backside power rail technology. The initial monthly production capacity is also expected to be around 30,000 wafers.
According to previous disclosures made by TSMC during financial calls, the company has developed a backside power rail solution for the N2 process, which is particularly suitable for high-performance computing (HPC) applications. This innovative technology is expected to boost speed by 10% to 12% and increase logic density by 10% to 15%. TSMC plans to introduce the backside power rail solution to customers in the latter half of 2025, with mass production scheduled for 2026. This timetable aligns with recent rumor circulating in the supply chain.
In addition to the latest progress on the N2P process, TSMC made an official announcement at the IEEE International Electron Devices Meeting (IEDM) on December 12th. Specifically, the company revealed its plans to introduce a 1.4nm process as the successor to the 2nm process. As reported by Tom’s Hardware, this new process, named A14, continues the naming convention from the 2nm process (A20). Production using the A14 process is anticipated to take place between 2027 and 2028.
(Image: TSMC)
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