As TSMC speed up its global expansion, the developments in its overseas fabs and the appointments of key leaders are under intense scrutiny. According to reports from DeepTech’s Voice, TSMC is said to choose Ray Chuang as the General Manager/CEO for its Fab in Germany. Chuang is considered a rising star promoted from the 18A fab manager to Vice President of Fab Operations I in this year.

Ray Chuang, a TSMC veteran since 1997, originally served as the senior manager of the 18A fab, showcasing expertise in various process technologies. Notably, he successfully led teams in the mass production of N5 and N4 process. He was elevated to Vice President of the Fab Operations I in May, 2023.

The unveiling of fab managers for TSMC’s overseas sites is progressing. In addition to the already disclosed appointments of Rick Cassidy and Dr. Y.L. Wang as Chairman and CEO of the Arizona fab, respectively, the Japanese fab (JASM) will see Vice President Y.H. Liaw, responsible for mature process production, taking the helm as CEO, according to the press release from Taiwan OCAC.

Potential Impacts May Postpone TSMC’s Fab in Germany Progress

TSMC’s plan includes the establishment of a subsidiary, European Semiconductor Manufacturing Company (ESMC) GmbH, set to build a fab in Dresden, eastern Germany. The total investment stands at EUR 10 billion, with an expected subsidy of about EUR 5 billion from the German government. Noteworthy partners in this venture, including Infineon, NXP, and Bosch, will each hold a 10% stake, while TSMC retains substantial control with over 50% ownership. The fab’s primary focus will be on producing automotive chips using 28nm/22nm processes, with an estimated capacity of 30,000 to 50,000 wafers.

The fab in Germany was initially expected to receive an EUR 5 billion subsidy, with production scheduled for 2027. However, a report from Reuters on November 23rd highlighted a ruling by the Germany’s Constitutional court that the German government’s re-location of EUR 60 billion from the pandemic fund to the climate transition fund was unconstitutional. Consequently, the German Ministry of Finance issued an emergency notice, freezing spending plans across various federal budgets. This unexpected move may impact the subsidies initially earmarked for TSMC fab in Germany.

Insights from TrendForce indicate that ESMC’s total planned production capacity is approximately 40Kwspm. The fab is set to focus on 28/22nm and 16/12nm processes, with groundbreaking expected in the latter half of 2024 and full-scale production in 2027. Forecast from TrendForce suggest that TSMC’s overseas capacity share (includes China), will rise from 9% in 2023 to 15% by 2027.
(Image: TSMC)

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According to TechNews’ report, Apple, NVIDIA, AMD, Qualcomm, and MediaTek all utilize TSMC’s semiconductor processes for manufacturing their latest chips, with some potentially employing Samsung’s foundry, though typically not for flagship products.

With Samsung’s improved yield rates in recent months, the company is eager to secure a portion of the orders, particularly for the 3-nanometer GAA (Gate-All-Around) process.

Earlier market reports suggested that Qualcomm’s Snapdragon 8 Gen 4 might adopt a dual-foundry strategy, simultaneously utilizing TSMC’s N3E process technology and Samsung’s SF3E process technology.

However, both Qualcomm and MediaTek currently plan to employ TSMC’s second-generation 3-nanometer process technology (N3E) for manufacturing chips like the Snapdragon 8 Gen 4 and Dimensity 4, without pursuing a dual-foundry strategy at this time.

As of the end of June 2022, Samsung announced the commencement of production for 3-nanometer process chips at its Hwaseong Industrial Complex in South Korea. These chips incorporate a new GAA transistor architecture technology, rumored to be more energy-efficient compared to TSMC’s 3-nanometer FinFET technology. Despite this, in the realm of 3nm, Samsung has yet to secure substantial orders from major clients.

Interestingly, the company has seen more success in the 4nm domain. It is reported that Samsung has gradually addressed yield and various issues in the 4-nanometer process technology domain. The third generation of 4-nanometer process technology has seen improvements in performance, reduced power consumption, increased density, and achieved yields close to TSMC’s level. Market sources indicate that Samsung has gained recognition from companies like AMD and Tesla, securing new orders.

Currently, TSMC’s 3-nanometer process technology production capacity is ramping up, with an expected monthly capacity of 100,000 wafers by the end of 2024. The revenue contribution is projected to increase from the current 5% to 10%.

Meanwhile, Samsung plans to introduce the second generation of its 3-nanometer process technology, named SF3 (3GAP), in 2024. Building upon the existing SF3E, it aims for further optimization, and Samsung’s in-house Exynos 2500 is expected to be one of the first high-performance chips to adopt this new process technology.

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• [News] Samsung Reportedly Lands a 4nm Mega Order – Why is AMD Switching to “Dual Foundry Mode” for Its Next-Gen Chips?
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According to TechNews’ report, during a recent financial conference, Samsung revealed its plans to diversify its sales structure by expanding its clientele in the fields of artificial intelligence semiconductors and automotive, moving away from its previous heavy reliance on the mobile sector.

As of 2023, it is understood that Samsung’s foundry sales distribution includes 54% from mobile, 19% from high-performance computing, and 11% from automotive.

According to a report from Wccftech, senior executives at Samsung have indicated that major players such as super-scale data centers, automotive original equipment manufacturers (OEMs), and other clients have been in contact with Samsung, considering the adoption of Samsung’s foundry services to manufacture their designed chips.

This includes the in-development 4-nanometer artificial intelligence accelerator and the 5-nanometer chips for the top-ranked electric vehicle company. Currently, Samsung is gearing up with its advanced packaging solution called SAINT (Samsung Advanced Interconnection Technology), aiming to compete with TSMC’s advanced packaging, CoWoS. Based on information disclosed by Samsung, there might be a collaboration with AMD in the field of artificial intelligence, involving the manufacturing of certain chips.

In fact, recent rumors suggest that Samsung has already reached an agreement with AMD to provide HBM3 and packaging technology for the upcoming Instinct MI300 series. Additionally, AMD might adopt a dual-sourcing strategy for the Zen 5 series architecture, choosing TSMC’s 3-nanometer process and Samsung’s 4-nanometer process technology for manufacturing the next-generation chips.

According to sources, besides the artificial intelligence domain, Samsung is likely to have received orders from the electric vehicle giant Tesla. The speculation points towards the possibility of fulfilling orders for Tesla’s next-generation HW 5.0 chip, designed for fully autonomous driving applications.

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• [News] Samsung Reportedly Lands a 4nm Mega Order – Why is AMD Switching to “Dual Foundry Mode” for Its Next-Gen Chips?

(Photo credit: Samsung)

Equipment is playing an indispensable role during the wafer manufacturing process. In response to market needs, the global EUV lithography supplier, ASML, has recently taken significant steps.

ASML’s Bold Move: Annual Investment of EUR 100 Million in Berlin Plant

As reported by the German media “Handelsblatt,” the Netherlands-based company ASML plans to invest EUR 100 million (USD 109 million) in 2023, with a similar annual investment in the subsequent years. This investment aims to enhance the production and development capabilities of ASML’s manufacturing plant located in Berlin, Germany.

Reports indicate that ASML’s Berlin plant primarily produced core components of EUV equipment, including wafer clamps, wafer tables, reticle chucks and mirror blocks. ASML acquired this facility, known as “Berliner Glas,” in 2020.

Foundries Actively Pursue EUV equipment

The EUV equipment plays a crucial role in manufacturing, utilizing specific wavelength light for radiation to precisely imprint images on wafers. Currently, the EUV equipment market is highly concentrated, with only a few global companies mastering this technology. Among them, Dutch company ASML stands out as the world’s largest and most advanced EUV company. Additionally, companies like Nikon, Canon, and Shanghai Micro Electronics Equipment (SMEE) are strategically positioning themselves in the EUV sector.

EUV technology, used for exposing semiconductor process, is indispensable due to its high cost, complex processes, and limited supply. ASML is the sole global supplier of EUV. For advanced processes below 7nm, EUV serves as an essential device. Developed over more than 20 years, EUV technology has become the cornerstone of advanced processes, enabling the continuation of Moore’s Law for at least another decade.

As a crucial EUV equipment supplier, ASML is working on a new generation of NA-EUV equipment, where “NA” represents numerical aperture. A higher NA value means a higher achievable resolution, allowing for more transistors on the chip. It is expected that by the year-end, ASML will unveil the world’s first high-NA EUV and deliver it to Intel.

Currently, both TSMC and Samsung utilize EUV equipment for manufacturing, covering TSMC’s 7nm, 5nm, and 3nm processes and Samsung’s EUV Line (7nm, 5nm, and 4nm) located in Hwaseong, Korea, along with the 3nm GAA process.

TSMC’s 2nm process will continue to leverage EUV technology. In a previous announcement in September, TSMC disclosed the acquisition of Intel’s subsidiary IMS for up to US 432.8 million, focusing on the research and production of electron beam lithography machines. Industry experts believe that TSMC’s move ensures the technical development of critical equipment and meets the supply demand for the commercialization of 2nm.

Following 2nm chips. Samsung plans to achieve mass production of 2nm processes in the mobile field by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively. According to the report in September, Samsung is gearing up to secure the yield of the next-generation EUV equipment, High-NA, with the prototype expected to launch later this year and official supply next year.

After announcing its return to the foundry business, Intel revealed in October that it has commenced mass production of Intel 4 process nodes using EUV technology. Currently, both Intel 7 and Intel 4 have achieved mass production, and Intel 3 is progressing according to plan, with the goal of completion by the end of 2023.

(Image: ASML)

Microsoft announced the in-house AI chip, Azure Maia 100, at the Ignite developer conference in Seattle on November 15, 2023. This chip is designed to handle OpenAI models, Bing, GitHub Copilot, ChatGPT, and other AI services. Support for Copilot, Azure OpenAI is expected to commence in early 2024.

TrendForce’s Insights:

1. Speculating on the Emphasis of Maia 100 on Inference, Microsoft’s Robust Ecosystem Advantage is Poised to Emerge Gradually

Microsoft has not disclosed detailed specifications for Azure Maia 100. Currently, it is known that the chip will be manufactured using TSMC’s 5nm process, featuring 105 billion transistors and supporting at least INT8 and INT4 precision formats. While Microsoft has indicated that the chip will be used for both training and inference, the computational formats it supports suggest a focus on inference applications.

This emphasis is driven by its incorporation of the less common INT4 low-precision computational format in comparison to other CSP manufacturers’ AI ASICs. Additionally, the lower precision contributes to reduced power consumption, shortening inference times, enhancing efficiency. However, the drawback lies in the sacrifice of accuracy.

Microsoft initiated its in-house AI chip project, “Athena,” in 2019. Developed in collaboration with OpenAI. Azure Maia 100, like other CSP manufacturers, aims to reduce costs and decrease dependency on NVIDIA. Despite Microsoft entering the field of proprietary AI chips later than its primary competitors, its formidable ecosystem is expected to gradually demonstrate a competitive advantage in this regard.

2. U.S. CSP Manufacturers Unveil In-House AI Chips, Meta Exclusively Adopts RISC-V Architecture

Google led the way with its first in-house AI chip, TPU v1, introduced as early as 2016, and has since iterated to the fifth generation with TPU v5e. Amazon followed suit in 2018 with Inferentia for inference, introduced Trainium for training in 2020, and launched the second generation, Inferentia2, in 2023, with Trainium2 expected in 2024.

Meta plans to debut its inaugural in-house AI chip, MTIA v1, in 2025. Given the releases from major competitors, Meta has expedited its timeline and is set to unveil the second-generation in-house AI chip, MTIA v2, in 2026.

Unlike other CSP manufacturers, both MTIA v1 and MTIA v2 adopt the RISC-V architecture, while other CSP manufacturers opt for the ARM architecture. RISC-V is a fully open-source architecture, requiring no instruction set licensing fees. The number of instructions (approximately 200) in RISC-V is lower than ARM (approximately 1,000).

This choice allows chips utilizing the RISC-V architecture to achieve lower power consumption. However, the RISC-V ecosystem is currently less mature, resulting in fewer manufacturers adopting it. Nevertheless, with the growing trend in data centers towards energy efficiency, it is anticipated that more companies will start incorporating RISC-V architecture into their in-house AI chips in the future.

3. The Battle of AI Chips Ultimately Relies on Ecosystems, Microsoft Poised for Competitive Edge

The competition among AI chips will ultimately hinge on the competition of ecosystems. Since 2006, NVIDIA has introduced the CUDA architecture, nearly ubiquitous in educational institutions. Thus, almost all AI engineers encounter CUDA during their academic tenure.

In 2017, NVIDIA further solidified its ecosystem by launching the RAPIDS AI acceleration integration solution and the GPU Cloud service platform. Notably, over 70% of NVIDIA’s workforce comprises software engineers, emphasizing its status as a software company. The performance of NVIDIA’s AI chips can be further enhanced through software innovations.

On the contrary, Microsoft possess a robust ecosystem like Windows. The recent Intel Arc GPU A770 showcased a 1.7x performance improvement in AI-driven Stable Diffusion on Microsoft Olive, this demonstrates that, similar to NVIDIA, Microsoft has the capability to enhance GPU performance through software.

Consequently, Microsoft’s in-house AI chips are poised to achieve superior performance in software collaboration compared to other CSP manufacturers, providing Microsoft with a competitive advantage in the AI competition.

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