Against the backdrop of geopolitical influences, the concentration of advanced semiconductor manufacturing processes in Taiwan has raised concerns among international companies. According to TrendForce data, as of the end of 2024, over 70% of global advanced process manufacturing capacity is still located in Taiwan.

Governments worldwide have responded by offering generous subsidy policies to attract semiconductor foundries to establish plants locally. The dynamics of Taiwan’s semiconductor fabs in the global setting and changes in the global production landscape have become a focal point of industry attention.

Per TrendForce’s data, when considering the equivalent 12-inch wafer production capacity, in 2023, Taiwan held a global share of approximately 47%, followed by China at 26%, South Korea at 12%, the United States at 6%, Singapore at 4%, Japan at 2%, Germany at 1%, and others at 2%. By 2027, the distribution is expected to shift, with Taiwan’s share decreasing to 42%, China increasing to 28%, South Korea at 10%, the United States at 7%, Singapore at 6%, Japan at 3%, Germany at 2%, and others at 1%.

Examining recent developments in the overseas expansion of Taiwan’s semiconductor foundries, Powerchip Semiconductor Manufacturing Corporation (PSMC) has officially announced the establishment of its first 12-inch fab, JSMC, in Sendai, Miyagi Prefecture, Japan. According to TrendForce’s research, the plant is planned to have a total capacity of around 40Kwspm, starting with a 40nm node and gradually transitioning to 28nm, primarily serving domestic clients in Japan while seeking subsidies and tax incentives for semiconductor.

JSMC’s construction is scheduled to commence in 2024, with full-scale production expected by 2027. With the establishment of PSMC’s overseas fab, TrendForce estimates that PSMC’s overseas production capacity will grow from 0% in 2023 to 9% in 2027.

The progress of TSMC’s second fab in Kumamoto, Japan, has garnered significant industry attention recently. On another note, The German cartel office has approved Bosch, NXP, and Infineon’s investment in TSMC’s German fab, ESMC. Each company will acquire a 10% stake, while TSMC will retain substantial control with over 50% ownership.

According to TrendForce’s research, ESMC’s total planned capacity is around 40Kwspm, focusing on 28/22nm and 16/12nm processes, with construction expected to start in the second half of 2024 and mass production in 2027. TrendForce predicts that TSMC’s overseas production capacity will increase from 9% in 2023 to 15% in 2027.

As for UMC, TrendForce’s research indicates that the overseas production capacity is projected to increase from 42% in 2023 to approximately 47% by 2027. Additionally, UMC’s Fab12i in Singapore has a production capacity of approximately 60Kwspm, with plans for manufacturing processes ranging from 55/40nm to 28/22nm. Moreover, UMC’s Fab12M in Japan is expanding its capacity by around 10Kwspm in collaboration with Denso.

Regarding Vanguard International Semiconductor (VIS), it was previously reported by Nikkei that VIS plans to construct its first 12-inch wafer fab in Singapore, primarily focusing on the demand for automotive chips. However, VIS has not yet officially announced any related developments. According to TrendForce’s research, if VIS does not have new plans for investment in a 12-inch fab, its estimated spending required for the operation of various fabs in 2024 is approximately $94 million, representing a nearly 70% decrease compared to previous years.

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Rumors swirl around AMD’s upcoming chip architecture, codenamed “Prometheus,” featuring the Zen 5C core. As reported by TechNews, the chip is poised to leverage both TSMC’s 3nm and Samsung’s 4nm processes simultaneously, marking a shift in the competitive landscape from process nodes, yield, and cost to factors like capacity, ecosystem, and geopolitics, are all depends on customer considerations.

Examining yields, TSMC claims an estimated 80% yield for its 4nm process, while Samsung has surged from 50% to an impressive 75%, aligning with TSMC’s standards and raising the likelihood of chip customers returning. Speculation abounds that major players such as Qualcomm and Nvidia may reconsider their suppliers, with industry sources suggesting Samsung’s 4nm capacity is roughly half of TSMC’s.

Revegnus, a reputable X(formerly Twitter) source, unveiled information from high-level Apple meetings, indicating a 63% yield for TSMC’s 3nm process but at double the price of the 4nm process. In the 4nm realm, Samsung’s yield mirrors TSMC’s, with Samsung showing a faster-than-expected yield recovery.

Consequently, with Samsung’s significant improvements in yield and capacity, coupled with TSMC’s decision to raise prices, major clients may explore secondary suppliers to diversify outsourcing orders, factoring in considerations such as cost and geopolitics. Recent reports suggest Samsung is in final negotiations for a 4nm collaboration with AMD, planning to shift some 4nm processor orders from TSMC to Samsung.

Beyond AMD, the Tensor G3 processor in Google’s Pixel 8 series this year adopts Samsung’s 4nm process. Samsung’s new fabs in Taylor, Texas, sees its inaugural customer in its Galaxy smartphones, producing Exynos processors.

Furthermore, Samsung announced that U.S.-based AI solution provider Groq will entrust the company to manufacture next-generation AI chips using the 4nm process, slated to commence production in 2025, marking the first order for the new Texas plant.

Regarding TSMC’s 4nm clients, alongside longstanding partners like Apple, Nvidia, Qualcomm, MediaTek, AMD, and Intel, indications propose a potential transition to TSMC’s 4nm process for Tensor G4, while Tensor G5 will be produced using TSMC’s 3nm process. Ending the current collaboration with Samsung, TSMC’s chip manufacturing debut is anticipated to be delayed until 2025.

Last year, rumors circulated about Tesla, the electric vehicle giant, shifting orders for the 5th generation self-driving chip, Hardware 5 (HW 5.0), to TSMC. This decision was prompted by Samsung’s lagging 4nm process yield at that time. However, with Samsung’s improved yield, industry inclination leans towards splitting orders between the two companies.

Mature process foundries are locked in a battle to uphold a 60% capacity utilization rate. Reports indicate that major players, including UMC, Vanguard International Semiconductor (VIS), and PSMC, are slashing prices significantly for the first quarter of the coming year to salvage their capacity utilization rates. This reduction, reaching double-digit percentages and up to 15% to 20% for project customers, stands out as the most extensive post-pandemic price cut, according to UDN News.

Post-Pandemic Price Challenges in Mature Process Foundries    

This pricing adjustment is pushing the prices of mature process foundries to a new low post-pandemic, affecting the profit margins and profitability trends of related companies. Industry sources disclose that only TSMC’s prices remain robust, with almost no exception for other foundries.

To rescue capacity utilization rates, companies are aggressively tweaking their quotes. A source from an IC design company privately reveals that foundries have notified them of slow-moving business in mature processes, resulting in a direct drop in capacity utilization rates. To ensure capacity utilization rates and market share, maintaining a certain level of production scale becomes imperative, prompting a substantial reduction in quotes.

Industry sources emphasize that despite recent indications of recovery in the PC and smartphone markets, clients remain cautious due to external factors such as inflation, especially given almost a year of inventory clearance. Companies, still on edge, fear slipping back into the challenges of inventory clearance and thus maintain a conservative approach to order placement.

Currently, the recovery in order placement strength is only about 30% to 40% of pre-pandemic levels, compelling wafer foundries to intensify their price cuts to prevent orders from being lost to competitors willing to lower prices, resulting in even lower capacity utilization.

It is evident that consumer IC demand for foundry services is low, and whom focusing on 8-inch mature process are the most affected. It is mainly due to excessive duplicate orders from integrated device manufacturers (IDMs) and IC design companies in the past, leading to inventory clearance for chips such as power management ICs, driver ICs, and microcontrollers (MCUs). Some products have even shifted to 12-inch wafers, keeping the capacity utilization rates of 8-inch foundries at a low level.

Navigate Semiconductor Shifts in TSMC, UMC, VIS, and PSMC

Industry sources note that TSMC is bolstered by advanced processes, enabling them to bundle them with mature processes for sale. Moreover, TSMC’s pricing strategy for mature processes has not surged as dramatically as that of other related companies, making it more acceptable to customers.

As for UMC, the company anticipates a drop in capacity utilization rates from 67% in the last quarter to 60% to 63% in this quarter, reaching a single-season low in recent years. Due to the continuous adjustment of capacity utilization rates, the gross profit margin will drop from 35.9% last quarter to 31% to 33%, reverting to levels seen at the beginning of the pandemic in 2021.

In response to pricing issues, UMC stated that, as mentioned in a recent earnings call, there will indeed be a significant decrease in the 8-inch, but there will be no adjustments for the 12-inch. Supply chain sources reveal that UMC has reportedly offered a 5% concession, aiming to consolidate order momentum with major clients this quarter. Considering the anticipated weak demand in the first quarter of next year and to attract more order placements, UMC plans to expand the price reduction to double-digit percentages.

According to the supply chain, VIS is expected to see a price reduction of up to 5% in the second half of the year. Large-volume clients may even secure a 10% discount, with a further decrease expected in the first quarter of next year, ranging from single to double-digit percentages. The company’s management previously mentioned at a conference call that, in response to intense price competition, short-term flexible adjustments are anticipated.

Similarly impacted by conservative customer order placements, PSMC reported losses in the third quarter, with capacity utilization rates hovering around 60%. It is reported that PSMC is also gearing up to implement price reduction measures to enhance capacity utilization rates.

(Image: VIS)

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The demand for TSMC’s CoWoS advanced packaging is skyrocketing. Following NVIDIA’s expansion confirmation in October, there are reports in the industry that major clients like Apple, AMD, Broadcom, Marvell, and others are also placing additional orders with TSMC.

To meet the demands of these five major clients, TSMC is fast-tracking the expansion of CoWoS advanced packaging capacity. Next year, the monthly capacity will increase by about 20% more than the original doubling target, reaching 35,000 wafers, reported by UDN News.

TSMC has not commented on the capacity deployment for CoWoS advanced packaging. Industry sources believe that the substantial orders from TSMC’s major clients indicate a widespread growth in AI applications, driving the demand for chips such as GPU and AI accelerators.

In response to the continuous increase in AI demand, TSMC had previously announced the doubling of CoWoS advanced packaging capacity expansion for next year but did not disclose the monthly production capacity. Industry reports suggest that TSMC’s CoWoS advanced packaging capacity next year will not only double but will also increase by an additional 20% from the original target, resulting in a total monthly capacity of 35,000 wafers.

NVIDIA currently stands as the main large customer for TSMC’s CoWoS advanced packaging, securing almost 60% of TSMC’s related capacity, which is used in its AI chips such as H100 and A100. Additionally, AMD’s latest AI chip products are in the mass production stage, and the upcoming MI300 chip, expected to launch next year, will adopt both SoIC and CoWoS advanced packaging.

At the same time, Xilinx, a subsidiary of AMD, has been a significant customer for TSMC’s CoWoS advanced packaging. With the continuous growth in AI demand, not only Xilinx but also Broadcom has started increasing orders for TSMC’s CoWoS advanced packaging capacity.

(Image: TSMC)

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Akira Amari, a Japanese lawmaker and leader of the parliamentary association to promote semiconductor strategy, reveals that Japan is gearing up to allocate a subsidy of up to 900 billion yen for the second-phase expansion of TSMC’s Kumamoto fab. The plan involves transitioning from the 22/28 nm and 12/16 nm processes to the more advanced 7 nm process. Once completed, Japan is anticipated to emerge as the leading semiconductor supply hub globally.

Media reports suggest that the cabinet amendment is expected to allot a total of 1.9 trillion yen for semiconductor subsidies in Japan. Japanese companies are slated to receive 590 billion yen, while TSMC’s second-phase expansion project in Kumamoto is in line for the highest subsidy of 900 billion yen, surpassing the market’s earlier projection of 760 billion yen.

Highlighting the unprecedented nature of this subsidy, Amari underscores the imperative of ensuring companies’ operational profitability. Japan envisions becoming a pivotal player in the semiconductor supply chain. Furthermore, contingent on the development scenario, the government is committed to evaluating subsidy reductions, with a pledge to support various schemes for establishing Japan as a long-term semiconductor hub.

As of now, the construction of TSMC’s first-phase fab in Kumamoto is advancing rapidly, with the total workforce anticipated to surpass a thousand. The team is preparing for a timely production launch in 2024.

Although the Kumamoto fab’s announcement and construction preceded that of the U.S. Arizona fab, set to commence production in 2025, TSMC’s Kumamoto fab is garnering robust support from official Japanese channels and partners including SONY Semiconductor Solutions and Denso. The fab is set to utilize 22/28 nm and 12/16 nm processes, with a total capital expenditure of 8.6 billion USD. The Japanese Ministry of Economy, Trade and Industry(METI) granted approval for a subsidy of 476 billion yen in June 2022, which represents approximately 40% of total capital expenditure is supported by the subsidy.

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