On October 11th, Amkor announced the official opening of its factory located in the Yen Phong 2C Industrial Park in Bac Ninh Province, Vietnam. The new facility, occupying 57 acres, is set to become Amkor’s largest, with an investment of approximately $1.6 billion by 2035. The factory primarily focuses on providing advanced system-level packaging and testing solutions to meet the semiconductor industry’s demand for advanced packaging. However, the company has not disclosed the factory’s current production and capacity.

Multiple Players Pursue CoWoS

The ongoing AI trend continues to drive demand for Chip-on-Wafer-on-Substrate (CoWoS) technology, benefiting TSMC, which holds a significant share of CoWoS production orders. However, companies like ASE Group, Amkor, and UMC are also positioning themselves in the CoWoS packaging manufacturing space. Industry experts believe that given the current high demand for TSMC’s CoWoS production, part of this demand may potentially shift to Amkor’s factories.

Furthermore, the popular Nvidia AI chips, which are in high demand globally, utilize 2.5D packaging technology, a responsibility currently held by TSMC. Recently, Nvidia hinted at the mass production of new AI chips like the GH200 and general server chip L40S, with reports suggesting that L40S will not require 2.5D packaging. Instead, it will be shared among several backend packaging companies, including ASE, Amkor, and SPIL.

Industry source has noted the strong demand for CoWoS in the AI sector, and with TSMC’s CoWoS production capacity already unable to meet demand for several quarters, some demand may potentially shift to Amkor or Samaung’s facilities.

Amkor has announced plans to expand its advanced packaging CoWoS-like capacity. According to industry insiders, Amkor’s monthly production capacity for 2.5D advanced packaging is expected to reach approximately 3,000 wafers in early 2023, with estimates of reaching 5,000 wafers by the end of 2023 and aiming for a significant increase to 7,000 units by the end of 2024.

Additionally, ASE Group has announced its presence in advanced CoWoS-related packaging. With their fan-out chip-on-substrate (FOCoS-Bridge) packaging technology, ASE has been chosen by major chip design house to handle their backend packaging after CoW.

In mid-September, South Korean media reported that Samsung is set to introduce its FO-PLP 2.5D advanced packaging technology to catch up with TSMC in the field of advanced packaging for AI chips. Samsung’s Advanced Packaging (AVP) team began developing FO-PLP advanced packaging for 2.5D chip packaging, allowing the integration of System-on-Chip (SoC) and High Bandwidth Memory (HBM) into an interposer to create a complete chip.

It’s worth mentioning that Samsung’s FO-PLP 2.5D packaging is rectangular, while TSMC’s CoWoS 2.5D uses a circular substrate. Samsung’s FO-PLP 2.5D packaging avoids edge substrate losses and boasts higher production efficiency. However, due to the need to transplant chips from wafers onto rectangular substrates, the process is more complex.

CoWoS Demand Continues

CoWoS technology is a form of 2.5D and 3D packaging, where chips are stacked and then packaged onto a substrate, resulting in a 2.5D or 3D structure. This technology reduces chip space, while also decreasing power consumption and costs. CoWoS packaging is applied in high-performance computing, artificial intelligence, data centers, 5G, the Internet of Things, automotive electronics, and other fields.

TrendForce research indicates a growing demand for advanced packaging technologies for AI and HPC chips. Currently, TSMC’s CoWoS is the primary choice for AI server chip production. CoWoS packaging mainly consists of CoW (Chip on Wafer), integrating various logic ICs (such as CPUs, GPUs, ASICs, etc.) and HBM memory, while oS (On Substrate) integrates CoW elements using Solder bump interconnects and packages them on a substrate. These CoWoS packages become the primary computing units on server motherboards, together with other components like networks, storage, power supply units (PSUs), and other I/O units, forming complete AI server systems.

Explore more

• Advanced Packaging in High Demand, TSMC and OAST Increasing Equipment Orders
• Understanding the 3D Packaging Trends Pursued by TSMC, Intel and Samsung
• An In-Depth Explanation of Advanced Packaging Technology: CoWoS

(Photo credit: Amkor)

TSMC is set to conduct an investor meeting on the 19th, with Morgan Stanley, UBS, and Bank of America Securities releasing their latest reports ahead of the event. These reports highlight five main areas of interest:

1. Q4 Operational Outlook
2. Future Gross Margin Trends
3. Potential Adjustments to Full-Year Revenue Estimates and Capital Expenditure
4. Economic and Operational Outlook for the Coming Year
5. 2nm Production Plans

Despite market uncertainties surrounding factors such as end-market demand, the Chinese mainland’s economic trajectory, and semiconductor industry cycles, Morgan Stanley Securities anticipates a 10% QoQ increase in TSMC’s Q4 revenue. They attribute this to strong demand for AI GPUs and ASICs, urgent orders from products like smartphone system-on-chips (SoCs) and PC GPUs, as well as sustained demand for Apple’s iPhones. Additionally, the gross margin is expected to benefit from the depreciation of the New Taiwan Dollar, potentially reaching 53%, surpassing the market consensus of 52.2%.

Bank of America Securities similarly projects a 10% QoQ revenue growth for TSMC in Q4, with a gross margin estimate of 52.7%. UBS Securities, on the other hand, has adjusted its Q4 revenue growth forecast from 10% to 7% while maintaining their expectation of a 10% YoY decline in full-year revenue.

In terms of capital expenditures, Morgan Stanley Securities, taking into account factors such as Intel’s 3nm outsourcing and delays in the U.S. factory expansion, estimates that TSMC’s capital expenditures will remain around $28 billion for both this year and the next. UBS Securities, however, believes that due to a slower short-term business recovery, capital expenditures for this year and the next will be adjusted to $31 billion and $30 billion, respectively.

Explore More

• TSMC to Receive One More Year of Exemption Amid U.S. Chip Export Ban to China
• TSMC’s 2nm Fab in Kaohsiung Prepares for N2P Mass Production

(Photo credit: TSMC)

As reported by The Wall Street Journal today, Taiwan Semiconductor Manufacturing Company (TSMC) is poised to secure an additional one-year exemption from the United States. TSMC’s semiconductor facility in Nanjing, China, is expected to continue operations in the “foreseeable future” as long as significant technical upgrades are not undertaken.

U.S.’s Attitude towards Semiconductor Giants in Asia

The U.S. imposed a ban on chip exports to China in October of the previous year, restricting semiconductor equipment manufacturers using U.S. technology from exporting to China without obtaining a license.

On October 9th, the South Korean government revealed that both Samsung and SK Hynix have earned recognition as “Validated End-Users (VEUs)” by the U.S., granting them the ability to import specific U.S. chip manufacturing equipment into their existing Chinese facilities without further U.S. approval.

The status of TSMC’s designation as a “Certified End-User” remains undisclosed,  and the Taiwanese government has not made any public statements on this issue at this time.

South Korea’s Future Challenges after Secured U.S. Exemption

Over the preceding year, the South Korean government and related companies have been actively engaged in mediation with the U.S. government and will persist in their efforts during the extended one-year exemption. “In reality, we cannot evade political risks and geopolitical uncertainties,” stated Choi Sang-mook, Chief Secretary for Economic Affairs in the South Korean President’s Office.

Through back to September 22th, the U.S. Department of Commerce released the final regulations for the “Chip Act.” The rules indicate that subsidized chip manufacturers will enter into binding agreements with the U.S. Department of Commerce, limiting expansion and collaborative scientific research activities in countries including China. The restrictions for advanced processes and mature processes are set at 5% and 10%, respectively. This implies a severely restricted scope for expansion, and the future prospects for Samsung and SK Hynix’s continued growth in China remain uncertain.

Nevertheless, the U.S. decision to grant Samsung and SK Hynix an indefinite exemption bodes well for the semiconductor industry in China, the United States, South Korea, and the global semiconductor supply chain. As per Samsung’s statement, most of the uncertainties associated with its semiconductor production in China have been resolved. Meanwhile, SK Hynix underscores that this development bolsters the stability of the global semiconductor supply chain.

(Image: TSMC)

In the ongoing global race for advanced semiconductor technology, TSMC, the leader in semiconductor manufacturing services, continues its strides towards 2nm project. The Hsinchu’s Baoshan plant is set to commence equipment installation in Q2 2024, with mass production scheduled for Q4 2025, starting with a monthly output of around 30,000 wafers. Meanwhile, TSMC fab in Kaohsiung is organizing for N2P mass production, featuring backside power supply tech, a year after N2’s debut.

According to a report by Taiwan’s Money DJ, as previously shared by TSMC, the N2 process introduces a backside power rail solution, ideal for high-performance computing (HPC) applications. The backside power rail promises a 10% to 12% speed boost and a 10% to 15% logic density improvement. The aim is to introduce backside power rail to customers in H2 2025, aligning with supply chain reports.

Notably, Intel led the transition from planar transistors to FinFET, and now, with evolving technologies like MBCFET, BSPDN (Backside Power Delivery Network) based on Gate-All-Around (GAA) FET. Major players such as TSMC, Samsung, and Intel actively compete for leadership in the next-gen GAA technology, and have further presented promising and proactive technology roadmaps.

According to Samsung Semiconductor’s plans, they target to implement the 2nm process into mass production by 2025, with 1.4nm scheduled for 2027. Intel, adopting RibbonFET transistor architecture based on GAA technology, anticipates pilot production of the 20A version in H1 2024 and mass production of the 18A in 2025.

TSMC is in the process of constructing a semiconductor factory in Kikuyo-cho, Kumamoto Prefecture, Kyushu, Japan (referred to as Plant 1). Production is expected to commence in December 2024. Besides this facility, TSMC has shown interest in establishing a second plant in Japan (referred to as Plant 2). According to Japanese reports, the government is considering providing TSMC with a substantial subsidy of up to 900 billion Japanese Yen for Plant 2.

On October 4, during the Public-Private Partnership Forum on Increasing Domestic Investment led by Japanese Prime Minister Fumio Kishida, plans were announced for economic measures to be finalized within October. The Ministry of Economy, Trade, and Industry of Japan (METI) will request a budget of 3.4 trillion Japanese Yen to establish three funds supporting semiconductor production and research and development. These funds are the ” Research and Development Project of the Enhanced Infrastructures for Post-5G Information and Communication Systems,” the “Specified Semiconductor Funding Program,” and the “Ensuring Stable Supply Support Fund.”

As reported by Asahi Shimbun, sources suggest that the METI deems it necessary to grant 900 billion Japanese Yen in subsidies for TSMC’s proposed Plant 2, nearly 600 billion Japanese Yen for the “Rapidus” national team aiming to produce next-gen semiconductor chips domestically, and 700 billion Japanese Yen for traditional chips like Sony CMOS image sensors.

The Japanese government will allocate the required funds for these economic measures in the 2023 fiscal year supplementary budget. If the METI’s budget request is approved, the budget for semiconductor-elated activities in the 2023 fiscal year supplementary budget (3.4 trillion Japanese Yen) will be 2.6 times higher than that in the 2022 fiscal year supplementary budget (1.3 trillion Japanese Yen).

The Kishida administration also announced plans to ease land restrictions for crucial manufacturing facilities such as semiconductor plants during the forum. As early as December, local governments will be able to issue development permits for agricultural land, forests, and other areas.

Before that, local governments could only grant permits for industries related to food logistics, data centers, and plant facilities. Now, this is being expanded to include vital strategic materials. Furthermore, changing the land category from agricultural land often required approvals from multiple government departments, a process that could take more than a year. In the future, these procedures are expected to be shortened to around four months.

(Image: Briáxis F. Mendes (孟必思), CC BY-SA 4.0, via Wikimedia Commons)