According to a report by China’s media outlet Jiwei, Japanese officials recently released a photo of a meeting with Chairman Mark Liu of TSMC. Japan’s Minister of Economy, Trade, and Industry, Yasutoshi Nishimura, updated his personal X account on the 1st of the month and posted a photo of the meeting. In his post, he mentioned the meeting with Mark Liu and the progress at the Kumamoto factory.

“We had a meeting with Chairman Mark Liu of TSMC,” wrote Yasutoshi Nishimura on X. “TSMC, in collaboration with Sony and Denso through their joint venture JASM, is constructing a factory in Kumamoto as a critical national initiative to revitalize Japan’s semiconductor industry. Cooperation in Kumamoto is making progress, and Japanese materials and equipment manufacturers, along with other related companies, have announced new investments. We will continue to collaborate for future innovations.”

The JASM Kumamoto factory, which began construction in 2022, started using its office building in August of this year. Hundreds of employees have been gradually moving in, and from October, machinery and equipment will be progressively installed. The earliest small-scale trial production is expected in the second quarter of 2024, with full-scale production by the end of the year. The monthly production capacity will reach 45,000 12-inch wafers, and TSMC is not ruling out the possibility of expanding with a second Kumamoto factory.

Sources confirm that a group of TSMC equipment-related engineers has recently quietly arrived in Japan. They have received orientation materials officially starting work at the TSMC Kumamoto factory.

Industry sources suggest that TSMC is on track to achieve its goal of starting production at the Kumamoto factory by the end of next year, and possibly even ahead of schedule.

台湾のマーク・リュウTSMC会長と会談しました。熊本におけるTSMCとソニー・デンソー合弁会社JASMの工場建設は、日本の半導体産業の再興に向けた重要な国家プロジェクトです。熊本では、日本の素材・装置メーカーなど関連企業が続々と新しい投資を表明するなど連携が進んでいます。今後も将来のイノベー… pic.twitter.com/zAIYxiDESa

— 西村やすとし NISHIMURA Yasutoshi (@nishy03) October 1, 2023

(Photo credit: TSMC)

According to a report by Taiwan’s Economic Daily, TSMC is set to hold its Q3 earnings conference on October 19th. The market is eagerly anticipating insights from the company’s top executives on six key areas: the latest semiconductor market outlook, Q3 financial forecasts, the status of 3-nanometer chip orders, progress in advanced packaging expansion, capital expenditure updates, and the latest developments in the AI market.

During the conference, TSMC will also unveil its financial results for the previous quarter. Analysts are expecting TSMC’s Q3 consolidated revenue, when measured in USD, to grow by nearly 10%, with a chance of gross margin exceeding the company’s estimated median of 52.5%. This suggests that Q3 profits are likely to surpass those of Q2.

TSMC has already announced its combined revenue for July and August, which totaled NT$366.3 billion. Based on TSMC’s financial forecasts, Q3 consolidated revenue is expected to reach between $16.7 billion and $17.5 billion USD. Using an exchange rate of 30.8 NT dollars per USD, this translates to an expected consolidated revenue in NT dollars ranging from NT$514.4 billion to NT$539 billion.

In the first half of the year, TSMC’s capital expenditure was $9.94 billion in Q1 and $8.17 billion in Q2, totaling $18.11 billion. Securities analysts previously estimated that TSMC’s annual capital expenditure for this year could range from $32 billion to $36 billion USD, with the possibility of a decrease next year.

Some industry experts believe that as advanced manufacturing processes have advanced to 2 nanometers, the customer base for the latest processes has started to decrease. Looking at the 3-nanometer process that is already in mass production, only Apple is currently leading the adoption, while others like NVIDIA, Qualcomm, and MediaTek are expected to transition to the 3-nanometer process next year. As a result, TSMC is shifting its focus to expanding production in the more cost-effective advanced packaging sector, which is one of the key reasons for the decrease in TSMC’s capital expenditure.

Furthermore, TSMC is currently estimating that it will be the first to introduce an enhanced version of the 3-nanometer process next year, with expectations to transition to the 2-nanometer process by 2025, using a new Gate-All-Around (GAA) transistor architecture to replace the FinFET transistor architecture used for nearly a decade. This represents a significant step into a new generation of semiconductor technology. Additionally, capacity for advanced packaging is expected to double next year.

(Photo credit: TSMC)

While 2nm advanced semiconductor chips are yet to enter mass production, the battle for equipment among semiconductor foundries is already in full swing.

TSMC, Samsung, and Rapidus Make Their Moves

To ensure the smooth deployment of 2nm process technology, TSMC, Samsung, and Rapidus have all embarked on pursuits in the upstream equipment sector.

TSMC, on September 12th, announced its intention to acquire a 10% stake in IMS Nanofabrication, a subsidiary of Intel, for no more than $432.8 million. IMS specializes in the development and production of electron beam lithography machines, widely used in semiconductor manufacturing, optical component production, MEMS manufacturing, and more. Industry experts believe that TSMC’s acquisition of IMS will ensure the development of critical equipment technology and meet the supply requirements for the commercialization of 2nm.

On the other hand, Samsung previously acquired a 3% stake in ASML, still holding approximately 0.7% of ASML shares. Additionally, Samsung’s collaboration with ASML continues to deepen. Reports suggest that Samsung is preparing to secure production of the next-generation High-NA EUV lithography machine, with the prototype expected to be unveiled later this year and commercial availability in the following year.

As for the semiconductor newcomer, Rapidus, obtaining ASML’s support is essential, given that EUV is a vital technology for mass-producing chips below 5-7nm. The latest reports from Japanese media indicate that ASML will establish a technical support base in Hokkaido, Japan, in 2024 and dispatch about 50 engineers to assist in setting up EUV lithography equipment in Rapidus’ 2nm chip factory’s pilot production line, offering assistance in commissioning, maintenance, and inspection.

The development of the major manufacturers in 2nm will be revealed in 2025

Leading traditional semiconductor foundries TSMC and Samsung, along with the emerging player Rapidus, are all actively positioning themselves in the 2nm chip landscape. So, how are these three companies progressing?

TSMC is targeting the production of N2 technology by 2025. Reports from June indicated that TSMC is fully committed, initiating preliminary preparations for the trial production of 2nm chips. In July, the TSMC supply chain revealed that TSMC had informed equipment suppliers to begin deliveries of 2nm-related machinery starting in the third quarter of the following year. In September, media reports revealed that TSMC had formed a dedicated 2nm task force, aiming to achieve risk production next year and commence mass production by 2025.

In June, Samsung announced its latest foundry technology innovations and business strategies, unveiling detailed plans and performance levels for 2nm process mass production. They plan to apply the 2nm process to mobile applications by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively.

According to Rapidus’ plan, trial production of 2nm chips is set to begin in 2025, with mass production slated for 2027. In July, Rapidus President Atsuyoshi Koike stated that operating a trial production line in 2025 and commencing mass production in 2027 is an ambitious goal, but progress is on track. He noted that once the company’s 2nm process products go into mass production, their unit price will be ten times that of current Japanese-produced logic semiconductors.

With this timeline, it appears that the 2nm chips from these three semiconductor giants will first make their debut in 2025. At that time, the competition for advanced 2nm processes is expected to become even more intense.

(Photo credit: TSMC)

According to a report by China’s Jiwei, Intel’s recent sale of a 10% stake in IMS to TSMC has not generated much buzz in the industry. Most industry insiders view this transaction positively, considering the importance of IMS and TSMC’s vertical integration.

However, why did TSMC decide to purchase a 10% stake in IMS now, when the two companies have been collaborating on research and development for a decade?

The Importance of IMS

When it comes to semiconductor equipment, Dutch lithography giant ASML is a well-known name. However, it’s worth noting that in the semiconductor manufacturing process, the multi-beam mask writer provided by IMS is also crucial. Established in Vienna in 1985, IMS primarily focuses on advanced process node photomask manufacturing.

The significance of photomasks is undeniable. As processes evolve, the demand for photomasks continues to rise. It’s understood that the 14nm process requires approximately 60 photomasks, while the 7nm process demands around 80 to even hundreds of them. Correspondingly, photomask prices have been steadily climbing. According to IBS data, photomask costs are approximately $5 million in the 16/14nm process, but in the 7nm process, they rapidly increase to $15 million.

Within the total cost of photomasks, which includes equipment like writers and inspection tools, raw materials like quartz and photoresist, as well as software like OPC and MDP, the writer’s contribution is significant.

Experts analyze that without IMS’ multi-beam mask writer, all EUV process technologies would come to a halt, rendering ASML’s EUV equipment less useful. Furthermore, as lithography technology advances towards High-NA EUV, its progress relies on sophisticated mask writing tools. With advanced processes continually pushing forward, IMS technology will play a crucial role.

Perhaps recognizing the importance of mask writers early on, Intel invested in IMS as early as 2009 and ultimately acquired it in 2015. After years of effort, IMS has secured a dominant position in the multi-beam mask writer market, with reported its employees and capacity quadrupling since the acquisition, bringing substantial profits to Intel.

Delving deeper, there is a longstanding connection between TSMC and IMS.

Since 2012, TSMC has been collaborating with IMS to develop multi-beam mask writers for advanced technology nodes. Kevin Zhang, Senior Vice President, Business Development and Overseas Operations Office at TSMC, stated that this investment will continue their long-term partnership to accelerate innovation and achieve deeper cross-industry collaboration.

Regarding TSMC’s investment in IMS, research institutions have pointed out that TSMC has always pursued a vertical integration strategy to master various aspects of technology and resources in the semiconductor manufacturing field. Particularly noteworthy is TSMC’s in-house mask manufacturing, where the precision and quality of masks are crucial for chip performance. IMS can be seen as a key supplier to TSMC, providing critical products.

Industry experts also point out that TSMC’s decision may help them gain an advantage in the 2nm competition. As the competition in the 2nm transitions from three competitors to four, involving TSMC, Samsung, Intel, and Japan’s Rapidus, 2025 is poised to be a pivotal year. In the era of 2nm, not only will the use of ASML’s next-generation High-NA EUV equipment be essential, but also harnessing the power of mask writers. TSMC’s investment in IMS could solidify their collaboration and help them pull ahead of other competitors.

(Photo credit: IMS)

According to a report from Taiwan’s Economic Daily, TSMC’s 3-nanometer technology has attracted another heavyweight client. Following Apple and MediaTek, it is rumored that Qualcomm will also commission TSMC to produce its next-generation 5G flagship chip using the 3-nanometer process. The chip is expected to be unveiled in late October, making Qualcomm the third client for TSMC’s 3-nanometer technology.

In response to these rumors, Qualcomm has not provided any comments, while TSMC has chosen to remain silent. Industry experts speculate that TSMC’s 3-nanometer technology will likely attract additional orders from major players such as NVIDIA and AMD in the future. With various leading-edge fabs continuously seeking TSMC’s services, it appears that TSMC’s 3-nanometer technology remains the top choice for international giants.

Last year, Qualcomm unveiled its annual 5G flagship chip, the “Snapdragon 8 Gen 2,” manufactured using TSMC’s 4-nanometer process. The previous-generation Snapdragon “8 Gen 1” was produced using Samsung’s 4-nanometer process, but it encountered issues related to heat dissipation. Consequently, Qualcomm released an upgraded version, the “Snapdragon 8+ Gen 1,” using TSMC’s 4-nanometer process.

Qualcomm has traditionally adopted a multi-supplier strategy for semiconductor manufacturing. It is rumored in the industry that Qualcomm has privately informed its smartphone brand customers about the upcoming next-generation 5G flagship chip, the “Snapdragon 8 Gen 3,” expected to be announced in late October. This chip will be available in two process versions: TSMC’s 4-nanometer (N4P) and 3-nanometer (N3E).

(Photo credit: TSMC)