According to Taiwan’s Money DJ, the AI wave is showing no signs of slowing down. Led by NVIDIA, major players including AMD, Intel, and international chip giants are aggressively entering the AI arena, driving increasing demand for advanced packaging and advanced processes. Industry reports suggest that TSMC is reallocating several thousand personnel from its Hsinchu 12B plant to support its Longtan and Tainan 18B facilities in a bid to address the current urgent demands.

TSMC typically follows a process of initial research and development (R&D) stages for advancing its processes before handing them over to the mini-line teams and then proceeding to full-scale production. As a result, the 2nm process is slated for trial production in the second quarter of 2024, leaving a gap of approximately six months. It is rumored that TSMC is mobilizing staff from its Hsinchu 12B plant to provide support for the CoWoS-focused Longtan facility and the Tainan 18B plant, which is responsible for mass-producing the 3nm process, to address the immediate needs.

Equipment suppliers estimate that TSMC’s CoWoS production capacity is set to reach 12,000 to 14,000 wafers per month by the end of this year, with a projected doubling of production by 2024. By the end of that year, it is expected to reach at least 26,000 wafers per month, potentially even surpassing 30,000 wafers. Meanwhile, for the 3nm family, in addition to Apple and MediaTek, AMD, NVIDIA, Qualcomm, and even Intel are confirmed to adopt the N3 family of processes.

(Photo credit: TSMC)

According to a report by Taiwan’s Money DJ, there’s good news from TSMC regarding its 3nm node. Sources within the supply chain have disclosed that the number of new chip designs using the 3nm process, known as “New Tape-Outs” (NTOs), has surged. It’s confirmed that customers including MediaTek, AMD, NVIDIA, and Qualcomm will follow in Apple’s footsteps for mass adoption of the 3nm process in the next year (2024) and the subsequent year. By the second half of next year, the monthly production capacity for the 3nm family, including N3E, will increase from the current approximately 60,000 wafers to 100,000 wafers.

According to publicly available information from TSMC, the company began volume production of its first 3nm process node, N3, in the second half of last year. The enhanced version of the 3nm process, N3E, started production in the latter half of this year. There will also be extensions to the 3nm process, including N3P, N3S, and N3X. This year, Apple’s high-end A17 Pro chip for its iPhones was based on the initial N3 process.

Both TSMC and MediaTek previously announced their collaboration, with MediaTek developing new Dimensity products using TSMC’s 3nm process. The design phase, known as “Tape Out,” has been successfully completed, and mass production is scheduled for next year. Industry reports indicate that aside from Apple and MediaTek, AMD, NVIDIA, and Qualcomm are also confirmed to adopt the N3 family of processes. Intel is also on the list, with mass production planned for the year after next.

TSMC’s first-generation 3nm process currently has a monthly production capacity of about 60,000 wafers, serving Apple as its primary customer. TSMC has initiated a program known as “Continuous Improvement Plan” (CIP) for the 3nm process, referred to as N3B in the industry. Supply chain sources suggest that N3B’s capacity will be integrated into subsequent extended process nodes, such as N3E, which is expected to attract more customers. It is estimated that the overall 3nm monthly production capacity will reach 100,000 wafers by the second half of next year.

(Photo credit: TSMC)

According to a report by Taiwan’s Economic Daily, TSMC’s CoWoS advanced packaging capacity is running at full throttle. As they actively expand their production capabilities, there are reports of major customers like NVIDIA increasing their orders for AI chips. Additionally, industry giants like AMD and Amazon have rushed in with urgent orders.

In response to this urgent situation, TSMC is actively seeking equipment suppliers to expand its CoWoS machine procurement. Beyond TSMC’s existing production expansion goals, the company is further increasing its orders for equipment by an additional 30%, highlighting the ongoing fervor in the AI market.

It is reported that TSMC has sought assistance from equipment manufacturers such as Scientech, Allring, Grand Process Technology, E&R Engineering, and GP Group for this endeavor. They plan to complete the delivery and installation of the equipment by the first half of the coming year. The related equipment manufacturers are experiencing a surge in activity.

Industry sources reveal that TSMC’s CoWoS advanced packaging monthly production capacity is currently around 12,000 units. With their previous expansion efforts, they aimed to gradually increase this to 15,000 to 20,000 units per month. Now, with the addition of more equipment, they are looking at the possibility of reaching capacities of over 25,000 units per month, potentially even approaching 30,000 units. This substantial increase in production capacity positions TSMC to handle a significantly larger volume of AI-related orders.

Equipment providers have pointed out that NVIDIA is currently TSMC’s largest customer for CoWoS advanced packaging, accounting for 60% of the production capacity. Recently, in response to robust demand in AI computing, NVIDIA has increased its orders. Additionally, urgent orders from other customers such as AMD, Amazon, and Broadcom have started to pour in.

(Photo credit: TSMC)

According to Taiwan’s Business Next, as Moore’s Law gradually reaches its limits, semiconductor manufacturers are transitioning from 2D to 3D chip stacking and packaging to increase transistor counts for improved performance. The final step, “packaging,” has become crucial. In line with this trend, Intel has announced the industry’s first glass-based substrate for advanced packaging, breaking traditional constraints, with mass production expected between 2026 and 2030.

Intel’s glass-based substrate packaging technology has been in development for a decade and was unveiled at the 2023 Innovation Day in Silicon Valley, USA. Intel aims to achieve the goal of accommodating 1 trillion transistors within a single package by 2030 using advanced glass-based packaging.

The rise of the AI wave has driven the demand for accelerated computing, increasing the requirements for chip density. Intel argues that current substrate materials consume more power and are more prone to expansion and warpage compared to glass, which better aligns with future needs. Industry analysts have noted that TSMC also has similar solutions.

According to Intel, Glass substrates can tolerate higher temperatures, offer 50% less pattern distortion, and have ultra-low flatness for improved depth of focus for lithography, and have the dimensional stability needed for extremely tight layer-to-layer interconnect overlay. As a result of these distinctive properties, a 10x increase in interconnect density is possible on glass substrates. Further, improved mechanical properties of glass enable ultra-large form-factor packages with very high assembly yields.

Glass substrates’ tolerance to higher temperatures also offers chip architects flexibility on how to set the design rules for power delivery and signal routing because it gives them the ability to seamlessly integrate optical interconnects, as well as embed inductors and capacitors into the glass at higher temperature processing.

According to a report from China’s Changjiang Securities released in May, the application of glass substrates in advanced packaging has been validated, and glass manufacturer Corning has introduced related products.

On the other hand, in a report by China’s Changjiang Securities released in May, the application of glass substrates in advanced packaging has been validated, with glass manufacturer Corning introducing related products.

(Photo credit: Intel)

According to a report by Taiwan’s Liberty Times, Taiwan’s Ministry of Economic Affairs Investment Commission (MOEAIC) has given its approval for Taiwan Semiconductor Manufacturing Company (TSMC) to increase its investment in its Arizona subsidiary by an additional $4.5 billion, following a previous approval in March of this year for a $3.5 billion capital injection. The MOEAIC stated that this decision is expected to facilitate the continued growth of Taiwan’s semiconductor industry and strengthen the supply chain linkage between Taiwan and the United States.

On the 18th of this month, the MOEAIC approved a total of eight significant investment cases, including six foreign investments, totaling approximately $5.72 billion.

Among these foreign investment cases, TSMC’s injection of $4.5 billion into its Arizona subsidiary aims to provide operational funding for activities related to the manufacturing, sales, testing, and computer-aided design of integrated circuits and other semiconductor devices.

(Photo credit: TSMC)