According to a report by Taiwan’s Media TechNews, Taiwan’s leading semiconductor foundry, TSMC (Taiwan Semiconductor Manufacturing Company), experienced a significant 2.43% decline in its ADR (American Depositary Receipt) on the last trading day of the previous week in the U.S. stock market. This drop was attributed to media reports indicating that TSMC had requested its suppliers to delay equipment deliveries, subsequently affecting the stock prices of related semiconductor equipment companies. Furthermore, Goldman Sachs Securities has reduced its projections for TSMC’s capital expenditure over the next two years.

Goldman Sachs Securities noted that due to the slower-than-expected recovery in end-market demand, they have adjusted their revenue and capital expenditure estimates for TSMC and believe that both TSMC and UMC, another major semiconductor foundry, might delay their capacity expansion schedules. To enhance efficiency, these companies may also allocate equipment resources more effectively, reducing capital expenditures for 2024 and 2025.

Goldman Sachs Securities estimates that TSMC’s capital expenditure for 2023 will remain around $31.6 billion, with no adjustments made. However, due to the uncertainty surrounding demand recovery, TSMC is likely to reduce the pace of equipment procurement for advanced nodes. Instead, some of Taiwan’s equipment may be relocated to overseas production bases in Japan and the United States. Consequently, Goldman Sachs expects TSMC’s capital expenditure for 2024 to decrease from $28 billion to $25 billion, a 21% reduction compared to 2023. As for 2025, the capital expenditure projection has been adjusted from $36 billion to $35 billion.

Additionally, Goldman Sachs Securities has also lowered the utilization rates for TSMC’s 3nm process. Utilization rates for 2023 and 2024 have been adjusted from 40% and 71% to 36% and 65%, respectively, while the 2025 utilization rate is expected to remain unchanged at 78%. The production capacity for the 3nm process in 2024 and 2025 has also been revised from 80,000 and 90,000 wafers per month to 70,000 and 80,000 wafers per month.

(Photo credit: TSMC)

According to a report by Taiwan’s Central News Agency, Arm, the semiconductor company, made its debut on the U.S. stock market with its stock price surging nearly 25% on the first day. Taiwan Semiconductor Manufacturing Company (TSMC) participated in Arm’s initial public offering (IPO), potentially yielding over 7 billion New Taiwan Dollars in returns. However, industry experts assert that TSMC’s primary focus is not on stock gains; rather, their strategic investment aims to elevate the cost and barriers for clients seeking to transition their semiconductor manufacturing to other foundries.

TSMC’s strategic investments are not unprecedented. In the past, TSMC collaborated with Intel and Samsung to jointly invest in ASML to facilitate the development of extreme ultraviolet (EUV) lithography equipment, enabling TSMC to advance to an enhanced 7-nanometer manufacturing process.

Arm has been a long-term partner of TSMC, with cumulative shipments of Arm architecture chips exceeding 250 billion units and commanding a market share of over 99% in the smartphone industry.

Industry analysts speculate that if TSMC and Arm strategically collaborate, offering integrated services that allow customers to utilize Arm’s IP-designed products in conjunction with TSMC’s process IP, it would enhance customer service and simultaneously increase the cost and barriers for customers looking to switch to other semiconductor foundries, thereby improving customer stickiness.

Currently, Arm’s applications span across cloud infrastructure, automotive, IoT, and artificial intelligence (AI), and industry experts contend that, apart from traditional CPU leaders like Intel, Arm provides the most comprehensive and robust semiconductor intellectual property (IP) design solutions for chip designers.

(Photo credit: TSMC)

According to a report by China’s tech news outlet JIWEI, industry sources have revealed that TSMC’s Kumamoto semiconductor fab in Japan is expected to turn profitable in 2025, following mass production anticipated to commence by the end of 2024.

Industry sources suggest that TSMC has bolstered its deployment in Kumamoto, Japan, in cooperation with its ecosystem partners in Taiwan, to better support key local clients. This collaboration is expected to yield benefits starting early 2024 from TSMC’s new fab.

The decision behind TSMC’s establishment in Kumamoto has multiple facets. Firstly, it’s believed that Apple desires full-fledged support from TSMC for its major supplier, Sony. Secondly, TSMC has maintained a long-term mutually beneficial relationship with Japan, potentially enhancing its research capabilities in materials and ensuring stable production capacity. Lastly, the Japanese government’s subsidies for factory construction align with TSMC’s needs, significantly reducing operational risks due to long-term orders from Sony and automotive clients.

Supply chain reports indicate that TSMC’s Kumamoto fab has steadily completed cleanrooms and electromechanical integration. With water and power supplies progressively becoming available, the relocation is anticipated to begin on October 1st, with subsequent trial production activities. This investment represents the sole overseas expansion of TSMC that is progressing smoothly and ahead of schedule, with plans for official mass production in the coming year.

Recent details regarding TSMC’s second Japanese fab have surfaced, indicating a groundbreaking date around April 2024, with production slated to commence by late 2026. The total investment is expected to exceed 1 trillion Japanese yen, primarily for producing 12nm process chips.

(Photo credit: TSMC)

In recent years, with the rise of AI and 5G technologies leading to increasing computational demands, Silicon Photonics technology has once again become a focal point of discussion in the semiconductor industry.

TrendForce Perspective:

• Rewriting Semiconductor Development Rules with Silicon Photonics 

Since the development of the semiconductor industry, the industry’s trajectory has largely followed the development predicted by Gordon Moore – roughly doubling the number of transistors that can be accommodated on an integrated circuit approximately every two years. However, as chip sizes continue to shrink, chip architecture design is gradually being challenged. Semiconductor manufacturers, including TSMC, Samsung, and Intel, are striving to break through Moore’s Law as their goal. Others have publicly announced their focus on mature processes (the industry divides at 7nm, with 7nm and below considered advanced processes) and optimization of existing technologies.

However, even as manufacturers push the boundaries of Moore’s Law, leading to increased transistor density per unit area, signal loss issues inevitably arise during signal transmission since chips rely on electricity to transmit signals. Despite the increased transistor count, power consumption problems persist. Silicon Photonics technology, which replaces electrical signals with optical signals for high-speed data transmission, successfully overcomes this challenge, achieving higher bandwidth and faster data processing. With this approach, chips do not need to cram more transistors per unit area or pursue smaller nanometers and nodes. Instead, they can achieve higher integration and performance on existing processes, further advancing technology.

• Optimistic about Silicon Photonics Technology, but Breakthroughs Will Take Time

Currently, Silicon Photonics technology still faces various challenges, including alignment and coupling, thermal management, modulation and detection, expansion and integration, among others. Significant breakthroughs are unlikely in the short term, and major global manufacturers are still in the early development stages. In Taiwan, recent reports suggest that TSMC is actively venturing into Silicon Photonics technology. While TSMC has not officially confirmed this news, during the Silicon Photonics International Forum, a senior vice president from TSMC clearly stated, “If a good Silicon Photonics integration system can be provided, it can address the key issues of energy efficiency and AI computing power. This could be a Paradigm Shift, and we might be at the beginning of a new era.”

This suggests that TSMC is optimistic about the development of Silicon Photonics technology. Although Taiwanese companies have not formally announced their entry into the Silicon Photonics field, it is expected that with the explosive growth in demand for data transmission, storage, and computing driven by AI technology, Silicon Photonics will undoubtedly be a critical technology for future semiconductor development.

With the increasing demand for massive computing in fields such as AI, communication, and autonomous vehicles, the evolution of integrated circuits (ICs) has reached a physical limit under the premise of Moore’s Law. How can this limit be surpassed? The answer lies in the realm of optics. Currently, many domestic and international companies are actively embracing “Silicon Photonics” technology. When electronics meet photons, it not only addresses the signal transmission loss issue but is also considered a key technology that could usher in a new era, potentially revolutionizing the future world.

Integrated circuits (ICs) cram millions of transistors onto a single chip, performing various complex calculations. Silicon Photonics, on the other hand, represents integrated “light” paths, where light-conductive pathways are consolidated. In simple terms, it is a technology that converts “electronic signals” into “optical signals” on a silicon platform, facilitating the transmission of both electrical and optical signals.

As technology rapidly advances and computer processing speeds increase, communication between chips has become a critical factor in computing performance. For instance, when ChatGPT was first launched, there were issues with lag and interruptions during the question and answer process, which were related to data transmission problems. Therefore, as AI technology continues to evolve, maintaining computational speed is a crucial aspect of embracing the AI era.

Silicon Photonics has the potential to enhance the speed of optoelectronic transmission, addressing the signal loss and heat issues associated with copper wiring in current computer components. Consequently, semiconductor giants such as TSMC and Intel have already invested in related research and development efforts. In this context, we interviewed Dr. Fang Yen Hsiang, director of the Opto-Electronics Micro Device & System Application Division and Electronic and Optoelectronic System Research Laboratories at the Industrial Technology Research Institute (ITRI), to gain insights into this critical technology.

What Is the Relationship Between Silicon Photonics and Optical Transceivers?

An optical transceiver module comprises various components, including optical receivers, amplifiers, modulators, and more. In the past, these components were individually scattered on a PCB (printed circuit board). However, to reduce power consumption, increase data transmission speed, and minimize transmission loss and signal delay, these components have been integrated into a single silicon chip. Fang emphasizes that this integration is the core of Silicon Photonics.

Integrated Circuits’ Next Step: The Three Stages of Silicon Photonics

• Silicon Photonics Stage 1: Upgrading from Traditional Pluggable Modules

Silicon Photonics has been quietly developing for over 20 years. The traditional Silicon Photonics pluggable optical transceiver modules look very much like USB interfaces and connect to two optical fibers—one for incoming and one for outgoing light. However, the electrical transmission path in pluggable modules had a long distance before reaching the switch inside the server. This resulted in significant signal loss at high speeds. To minimize this loss, Silicon Photonics components have been moved closer to the server’s switch, shortening the electrical transmission path. Consequently, the original pluggable modules now only contain optical fibers.

This approach aligns with the actively developing “Co-Packaged Optics” (CPO) technology in the industry. The main idea is to assemble electronic integrated circuits (EIC) and photonic integrated circuits (PIC) onto the same substrate, creating a co-packaged board that integrates chips and modules. This co-packaging, known as CPO light engines (depicted in figure “d” below), replaces optical transceivers and brings optical engines closer to CPU/GPU chips (depicted in figure “d” as chips). This reduces transmission paths, minimizes transmission loss, and reduces signal delay.

According to ITRI, this technology reduces costs, increases data transmission by over 8 times, provides more than 30 times the computing power, and saves 50% in power consumption. However, the integration of chipsets is still a work in progress, and refining CPO technology will be the next important step in the development of Silicon Photonics.

• Solving the CPO Bottleneck and Beyond – Silicon Photonics Stage 2: Addressing CPU/GPU Transmission Issues

Currently, Silicon Photonics primarily addresses the signal delay challenges of plug-in modules. As technology progresses, the next stage will involve solving the electrical signal transmission issues between CPUs and GPUs. Academics point out that chip-to-chip communication is primarily based on electrical signals. Therefore, the next step is to enable internal chip-to-chip communication between GPUs and CPUs using optical waveguides, converting all electrical signals into optical signals to accelerate AI computations and address the current computational bottleneck.

• Silicon Photonics Ultimate Stage 3: The Arrival of the All-Optical Network (AON) Era

As technology advances even further, we will usher in the era of the “All-Optical Network” (AON). This means that all chip-to-chip communication will rely on optical signals, including random storage, transmission, switching, and processing, all of which will be transmitted as optical signals. Japan has already been actively implementing Silicon Photonics in preparation for the full transition to all-optical networks in this context.

Where Does Silicon Photonics Currently Face Technological Challenges?

Currently, Silicon Photonics faces several challenges related to component integration. First and foremost is the issue of communication. Dr. Fang Yen Hsiang provides an example: semiconductor manufacturers understand electronic processes, but because the performance of photonic components is sensitive to factors such as temperature and path length, and because linewidth and spacing have a significant impact on optical signal transmission, a communication platform is needed. This platform would provide design specifications, materials, parameters, and other information to facilitate communication between electronic and photonic manufacturers.

Furthermore, Silicon Photonics is currently being applied in niche markets, and various packaging processes and material standards are still being established. Most of the wafer foundries that provide Silicon Photonics chip fabrication belong to the realm of customized services and may not be suitable for use by other customers. The lack of a unified platform could hinder the development of Silicon Photonics technology.

In addition to the lack of a common platform, high manufacturing costs, integrated light sources, component performance, material compatibility, thermal effects, and reliability are also challenges in Silicon Photonics manufacturing processes. With ongoing technological progress and innovation, it is expected that these bottlenecks will be overcome in the coming years to a decade.

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: Google)