With the increasing demand for massive computing in fields such as AI, communication, and autonomous vehicles, the evolution of integrated circuits (ICs) has reached a physical limit under the premise of Moore’s Law. How can this limit be surpassed? The answer lies in the realm of optics. Currently, many domestic and international companies are actively embracing “Silicon Photonics” technology. When electronics meet photons, it not only addresses the signal transmission loss issue but is also considered a key technology that could usher in a new era, potentially revolutionizing the future world.

Integrated circuits (ICs) cram millions of transistors onto a single chip, performing various complex calculations. Silicon Photonics, on the other hand, represents integrated “light” paths, where light-conductive pathways are consolidated. In simple terms, it is a technology that converts “electronic signals” into “optical signals” on a silicon platform, facilitating the transmission of both electrical and optical signals.

As technology rapidly advances and computer processing speeds increase, communication between chips has become a critical factor in computing performance. For instance, when ChatGPT was first launched, there were issues with lag and interruptions during the question and answer process, which were related to data transmission problems. Therefore, as AI technology continues to evolve, maintaining computational speed is a crucial aspect of embracing the AI era.

Silicon Photonics has the potential to enhance the speed of optoelectronic transmission, addressing the signal loss and heat issues associated with copper wiring in current computer components. Consequently, semiconductor giants such as TSMC and Intel have already invested in related research and development efforts. In this context, we interviewed Dr. Fang Yen Hsiang, director of the Opto-Electronics Micro Device & System Application Division and Electronic and Optoelectronic System Research Laboratories at the Industrial Technology Research Institute (ITRI), to gain insights into this critical technology.

What Is the Relationship Between Silicon Photonics and Optical Transceivers?

An optical transceiver module comprises various components, including optical receivers, amplifiers, modulators, and more. In the past, these components were individually scattered on a PCB (printed circuit board). However, to reduce power consumption, increase data transmission speed, and minimize transmission loss and signal delay, these components have been integrated into a single silicon chip. Fang emphasizes that this integration is the core of Silicon Photonics.

Integrated Circuits’ Next Step: The Three Stages of Silicon Photonics

• Silicon Photonics Stage 1: Upgrading from Traditional Pluggable Modules

Silicon Photonics has been quietly developing for over 20 years. The traditional Silicon Photonics pluggable optical transceiver modules look very much like USB interfaces and connect to two optical fibers—one for incoming and one for outgoing light. However, the electrical transmission path in pluggable modules had a long distance before reaching the switch inside the server. This resulted in significant signal loss at high speeds. To minimize this loss, Silicon Photonics components have been moved closer to the server’s switch, shortening the electrical transmission path. Consequently, the original pluggable modules now only contain optical fibers.

This approach aligns with the actively developing “Co-Packaged Optics” (CPO) technology in the industry. The main idea is to assemble electronic integrated circuits (EIC) and photonic integrated circuits (PIC) onto the same substrate, creating a co-packaged board that integrates chips and modules. This co-packaging, known as CPO light engines (depicted in figure “d” below), replaces optical transceivers and brings optical engines closer to CPU/GPU chips (depicted in figure “d” as chips). This reduces transmission paths, minimizes transmission loss, and reduces signal delay.

According to ITRI, this technology reduces costs, increases data transmission by over 8 times, provides more than 30 times the computing power, and saves 50% in power consumption. However, the integration of chipsets is still a work in progress, and refining CPO technology will be the next important step in the development of Silicon Photonics.

• Solving the CPO Bottleneck and Beyond – Silicon Photonics Stage 2: Addressing CPU/GPU Transmission Issues

Currently, Silicon Photonics primarily addresses the signal delay challenges of plug-in modules. As technology progresses, the next stage will involve solving the electrical signal transmission issues between CPUs and GPUs. Academics point out that chip-to-chip communication is primarily based on electrical signals. Therefore, the next step is to enable internal chip-to-chip communication between GPUs and CPUs using optical waveguides, converting all electrical signals into optical signals to accelerate AI computations and address the current computational bottleneck.

• Silicon Photonics Ultimate Stage 3: The Arrival of the All-Optical Network (AON) Era

As technology advances even further, we will usher in the era of the “All-Optical Network” (AON). This means that all chip-to-chip communication will rely on optical signals, including random storage, transmission, switching, and processing, all of which will be transmitted as optical signals. Japan has already been actively implementing Silicon Photonics in preparation for the full transition to all-optical networks in this context.

Where Does Silicon Photonics Currently Face Technological Challenges?

Currently, Silicon Photonics faces several challenges related to component integration. First and foremost is the issue of communication. Dr. Fang Yen Hsiang provides an example: semiconductor manufacturers understand electronic processes, but because the performance of photonic components is sensitive to factors such as temperature and path length, and because linewidth and spacing have a significant impact on optical signal transmission, a communication platform is needed. This platform would provide design specifications, materials, parameters, and other information to facilitate communication between electronic and photonic manufacturers.

Furthermore, Silicon Photonics is currently being applied in niche markets, and various packaging processes and material standards are still being established. Most of the wafer foundries that provide Silicon Photonics chip fabrication belong to the realm of customized services and may not be suitable for use by other customers. The lack of a unified platform could hinder the development of Silicon Photonics technology.

In addition to the lack of a common platform, high manufacturing costs, integrated light sources, component performance, material compatibility, thermal effects, and reliability are also challenges in Silicon Photonics manufacturing processes. With ongoing technological progress and innovation, it is expected that these bottlenecks will be overcome in the coming years to a decade.

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: Google)

According to a report by Taiwan’s Commercial Times, TSMC is facing a tight supply of advanced packaging capacity, with its Taichung factory ramping up equipment support at a rapid pace. Industry insiders have disclosed that TSMC’s annual production capacity for the backend CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging is only 150,000 to 300,000 units, falling short of customer demand by over 20%.

To address this shortfall, TSMC officially inaugurated its advanced packaging and testing Plant 6 in Zhunan in June. TSMC’s management has also committed to steadily increasing CoWoS production capacity each quarter, and third-party testing facilities are being actively engaged to bridge the gap.

It is worth noting that TSMC’s Longtan factory has traditionally been a key hub for CoWoS and InFO (Integrated Fan-Out) packaging, with a primary focus on InFO production at approximately 100,000 units per month and a smaller portion allocated to CoWoS. Although some of the InFO capacity has been relocated to the Southern Taiwan Science Park, Longtan’s physical space constraints continue to make Zhunan the primary location for CoWoS expansion. TSMC’s Taichung AP5 factory, on the other hand, is prioritizing WoS (Wafer-on-Substrate) expansion, with CoW (Chip-on-Wafer) expansion slated to commence next year. Many equipment suppliers have reportedly received urgent orders related to these expansion efforts.

Analysts estimate that this year’s overall CoWoS production will reach 110,000 units, doubling to 250,000 units next year. However, analysts caution that while TSMC currently dominates the CoWoS production landscape, other players are gradually entering the field. Therefore, it is crucial to monitor whether an oversupply situation may emerge in the mid-term next year.

(Photo credit: TSMC)

On August 29, 2023, Huawei quietly launched its new smartphone, the Huawei Mate 60 Pro, on its official website without the usual fanfare associated with new product releases. Unlike previous events or those held by other brands, Huawei chose to communicate with consumers solely through a letter. What intrigued the market most was the specification of the new device’s System-on-Chip (SoC). Initially, Huawei did not provide any official information about it. However, the release of this new smartphone demonstrates China’s determination to achieve semiconductor self-sufficiency.

Key Insights from TrendForce:

• Overcoming U.S. Sanctions, Huawei Makes a Comeback

In the past, Huawei secured its position as the second-largest player in the global smartphone market by leveraging the differentiating advantage of its in-house developed Kirin SoC chips. However, since May 2019, Huawei has been affected by U.S. sanctions. In September 2020, TSMC, which previously manufactured chips for Huawei, announced the cessation of production. With no supply from TSMC, Huawei’s inventory of 5G chips was depleted by the third quarter of 2022.

Unable to acquire high-end chips, Huawei’s market share in the smartphone industry saw a significant decline. The company could only source 4G chips not subject to U.S. sanctions from Qualcomm or UNISOC. It was believed that U.S. sanctions would severely impact Huawei’s smartphone supply chain and push the company into a dire situation. However, upon analyzing Huawei’s latest release, it is evident that the new smartphone not only features an in-house developed SoC chip by Huawei’s semiconductor subsidiary HiSilicon but also incorporates components and designs from various Chinese manufacturers.

• China’s Semiconductor Self-Sufficiency Continues to Strengthen, Minimal Impact on Taiwanese Supply Chain Expected

China’s pursuit of semiconductor self-sufficiency has become an inevitable outcome of industry development. Although Huawei has not provided detailed specifications for the SoC chip in the Mate 60 Pro, it is speculated that this chip likely uses SMIC’s N+2 process. Due to sanctions, SMIC has been unable to obtain essential EUV equipment. Furthermore, based on the chip’s performance benchmarking, it is comparable to Qualcomm’s flagship Snapdragon 888 chip released in 2021. This suggests that the SoC’s process technology likely falls in the range of 7-14nm, which still lags behind current advanced processes. Nevertheless, this achievement underscores China’s commitment to semiconductor self-sufficiency.

As China gains the ability to independently develop and produce chips, the question arises of whether other Chinese smartphone brands, apart from Huawei, will begin their own chip development efforts. Will this development impact Taiwanese IC design house and foundries that previously held related orders? MediaTek, for instance, primarily supplies chips to brands such as OPPO and vivo. Given that Huawei competes strongly with OPPO and vivo in the smartphone market, it is unlikely that these two brands will entrust their smartphone core SoCs to Huawei’s HiSilicon. Additionally, developing proprietary chips comes with significant costs. Therefore, under these circumstances, it is expected that OPPO and vivo will maintain their partnerships with MediaTek. MediaTek’s chip designs can also utilize TSMC’s advanced processes, giving OPPO and vivo a key competitive advantage against Huawei. Consequently, it is inferred that as long as there is a significant gap between the processes and yields of SMIC and TSMC, Taiwanese foundries will not be significantly affected.

(Photo credit: Huawei)

According to a report by Taiwan’s Economic Daily, AI is driving a massive demand for data transmission, and silicon photonics and Co-Packaged Optics (CPO) have become new focal points in the industry. TSMC is actively entering this field and is rumored to be collaborating with major customers such as Broadcom and NVIDIA to jointly develop these technologies. The earliest large orders are expected to come in the second half of next year.

TSMC has already assembled a research and development team of over 200 people, aiming to seize the business opportunities in the emerging market of ultra-high-speed computing chips based on silicon photonics, which are expected to arrive gradually starting next year.

Regarding these rumors, TSMC has stated that they do not comment on customer and product situations. However, TSMC has a high regard for silicon photonics technology. TSMC Vice President Douglas Yu recently stated publicly, “If we can provide a good silicon photonics integration system, it can address two key issues: energy efficiency and AI computing capability. This could be a paradigm shift. We may be at the beginning of a new era.”

Silicon photonics was a hot topic at the recent SEMICON Taiwan 2023 with major semiconductor giants like TSMC and ASE giving related keynote speeches. This surge in interest is mainly due to the proliferation of AI applications, which have raised questions about how to make data transmission faster and achieve signal latency reduction. The traditional method of using electricity for signal transmission no longer meets the demands, and silicon photonics, which converts electricity into faster optical transmission, has become the highly anticipated next-generation technology to enhance high-volume data transmission speeds in the industry.

Industry reports suggest that TSMC is currently collaborating with major customers like Broadcom and NVIDIA to develop new products in the field of silicon photonics and Co-Packaged Optics. The manufacturing process technology ranges from 45 nanometers to 7 nanometers, and with mass production slated for 2025. At that time, it is expected to bring new business opportunities to TSMC.

Industry sources reveal that TSMC has already organized a research and development team of approximately 200 people. In the future, silicon photonics is expected to be incorporated into CPU, GPU, and other computing processes. By changing from electronic transmission lines to faster optical transmission internally, computing capabilities are expected to increase several tens of times compared to existing processors. Currently, this technology is still in the research and academic paper stage, but the industry has high hopes that it will become a new driver of explosive growth for TSMC’s operations in the coming years.

(Photo credit: Google)

According to a report by Taiwan’s Money DJ, the production schedule for TSMC’s semiconductor foundry in the United States has been delayed until 2025, raising concerns among observers. However, Chairman Mark Liu, in an interview on the 6th, stated that there has been significant progress over the past five months and expressed confidence in the project’s success. Industry sources have indicated that TSMC’s U.S. facility may alter its ramp-up strategy by first establishing a mini-line for trial production, with the expectation of having it in place by the first quarter of 2024.

TSMC’s Fab 21 Phase 1 construction began in April 2021, originally slated for early 2024 production. However, challenges such as a shortage of skilled equipment installation personnel, local union protests, and differences in overseas safety regulations have caused delays in equipment installation. This has compelled TSMC to adjust its plans, and the expected production timeline is now set for 2025, representing a one-year delay.

Industry analysts have noted that the efficiency of equipment entering the facility at TSMC’s U.S. plant in Arizona is only about one-third of that of its Taiwan facilities. Given the current pace of progress, the time required for equipment setup to actual production could be substantial. Therefore, TSMC has decided to change its previous ramp-up strategy and first establish a mini-line with an initial estimated monthly capacity of about 4,000 to 5,000 wafers. This approach aims to ensure some level of production output while mitigating potential contract breach issues arising from delays in production.

(Photo credit: TSMC)