As applications like AIGC, 8K, AR/MR, and others continue to develop, 3D IC stacking and heterogeneous integration of chiplet have become the primary solutions to meet future high-performance computing demands and extend Moore’s Law.

Major companies like TSMC and Intel have been expanding their investments in heterogeneous integration manufacturing and related research and development in recent years. Additionally, leading EDA company Cadence has taken the industry lead by introducing the “Integrity 3D-IC” platform, an integrated solution for design planning, realization, and system analysis simulation tools, marking a significant step towards 3D chip stacking.

Differences between 2.5D and 3D Packaging

The main difference between 2.5D and 3D packaging technologies lies in the stacking method. 2.5D packaging involves stacking chips one by one on an interposer or connecting them through silicon bridges, primarily used for assembling logic processing chips and high-bandwidth memory. On the other hand, 3D packaging is a technology that vertically stacks chips, mainly targeting high-performance logic chips and SoC manufacturing.

CPU and HBM Stacking Demands

With the rapid development of applications like AIGC, AR/VR, and 8K, it is expected that a significant amount of computational demand will arise, particularly driving the need for parallel computing systems capable of processing big data in a short time. To overcome the bandwidth limitations of DDR SDRAM and further enhance parallel computing performance, the industry has been increasingly adopting High-Bandwidth Memory (HBM). This trend has led to a shift from the traditional “CPU + memory (such as DDR4)” architecture to the “Chip + HBM stacking” 2.5D architecture. With continuous growth in computational demand, the future may see the integration of CPU, GPU, or SoC through 3D stacking.

3D Stacking with HBM Prevails, but CPU Stacking Lags Behind

HBM was introduced in 2013 as a 3D stacked architecture for high-performance SDRAM. Over time, the stacking of multiple layers of HBM has become widespread in packaging, while the stacking of CPUs/GPUs has not seen significant progress.

The main reasons for this disparity can be attributed to three factors: 1. Thermal conduction, 2. Thermal stress, and 3. IC design. First, 3D stacking has historically performed poorly in terms of thermal conduction, which is why it is primarily used in memory stacking, as memory operations generate much less heat than logic operations. As a result, the thermal conduction issues faced by current memory stacking products can be largely disregarded.

Second, thermal stress issues arise from the mismatch in coefficients of thermal expansion (CTE) between materials and the introduction of stress from thinning the chips and introducing metal layers. The complex stress distribution in stacked structures has a significant negative impact on product reliability.

Finally, IC design challenges from a lack of EDA tools, as traditional CAD tools are inadequate for handling 3D design rules. Developers must create their own tools to address process requirements, and the complex design of 3D packaging further increases the design, manufacturing, and testing costs.

How EDA Companies Offer Solutions

Cadence, during the LIVE Taiwan 2023 user annual conference, highlighted its years of effort in developing solutions. They have introduced tools like the Clarity 3D solver, Celsius thermal solver, and Sigrity Signal and Power Integrity, which can address thermal conduction and thermal stress simulation issues. When combined with Cadence’s comprehensive EDA tools, these offerings contribute to the growth of the “Integrity 3D-IC” platform, aiding in the development of 3D IC design.

“3D IC” represents a critical design trend in semiconductor development. However, it presents greater challenges and complexity than other projects. In addition to the challenges in Logic IC design, there is a need for analog and multi-physics simulations. Therefore, cross-platform design tools are indispensable. The tools provided by EDA leader Cadence are expected to strengthen the 3D IC design tool platform, reducing the technological barriers for stacking CPU, GPU, or SoC to enhance chip computing performance.

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: TSMC)

According to Taiwan’s Economic Daily, TSMC Chairman Mark Liu stated on 9/6 that semiconductor technology development “has reached the exit of the tunnel, and there are more possibilities beyond the tunnel; we are no longer bound by the tunnel.”

Regarding TSMC’s progress in establishing a factory in the United States, Liu mentioned that this project has received support from the local government and has made significant progress in recent months. He added, “We will certainly make it very successful.”

As for the recent shortage of chips caused by generative AI, Liu noted that it is not due to TSMC’s manufacturing capacity but rather the sudden threefold increase in CoWoS (Chip-on-Wafer-on-Substrate) demand. TSMC will continue to support the demand in the short term but cannot immediately ramp up production. Liu estimated that TSMC’s capacity will catch up with customer demand in about a year and a half, considering the capacity bottleneck as a short-term phenomenon.

Regarding SoftBank Group’s subsidiary, Arm, planning an initial public offering (IPO) to raise funds, Liu also revealed that they are evaluating whether to become an investor in Arm, with a decision expected in the next one or two weeks. He emphasized Arm’s importance within the semiconductor ecosystem, expressing TSMC’s desire for a successful Arm IPO.

Huawei’s official website unexpectedly unveiled its latest flagship smartphone, the Mate 60 Pro, on August 29, 2023, followed by the release of the Mate 60 the next day. The Mate 60 Pro’s performance, powered by the Kirin 9000S SoC, has garnered significant attention in the market.

TrendForce’s Insights:

• Kirin 9000S Offers Comparable Computing Power to 2021 Flagships, But Energy Efficiency May Lag

According to benchmark test results from the Geekbench Browser, a product known as Huawei LNA-AL00, believed to be housing the Kirin 9000S, first appeared in test data on March 30, 2023, and has been continually updated since. The test results for Huawei LNA-AL00 during this period fall into two ranges. One range is roughly equivalent to the Qualcomm Snapdragon 8+ Gen 1, while the other is on par with the Qualcomm Snapdragon 888. This suggests potential variations in Kirin 9000S versions.

Further analysis of the Kirin 9000S reveals that its CPU architecture maintains the 1+3+4 configuration of the Kirin 9000 but operates at slightly lower clock speeds, with a difference of approximately 10-20%. The GPU is Huawei’s in-house Maleoon 910. However, in comparison to the Kirin 9000, which employs TSMC’s 5nm process, the Kirin 9000S has a larger chip size, roughly 30% larger. Additionally, the presence of a large Vapor Chamber beneath the Mate 60 Pro’s screen indicates that the Kirin 9000S may have higher energy consumption, reflecting the use of a less advanced process than TSMC’s 7nm. Overall, Kirin 9000S is expected to offer computing performance similar to mainstream flagships from 2021-2022, but its energy efficiency might align with levels seen in 2019-2020.

• Maintaining Performance Gap with Other Flagship SoCs Will Be a Key Challenge for Huawei and SMIC

Based on available information, Kirin 9000S is likely produced by SMIC. Currently, SMIC’s advanced process nodes include 14nm, N+1, and N+2. Since SMIC has indicated that the N+1 process is not equivalent to 7nm, it is speculated to fall between 10-8nm. To produce Kirin 9000S, it would need to utilize an N+2 process closer to 7nm, which is currently the most suitable process node for domestic wafer foundries in China.

Kirin 9000S undoubtedly represents the pinnacle of China’s domestic IC design and manufacturing capabilities. In terms of computing performance, it lags only 2-3 years behind Qualcomm and MediaTek’s upcoming flagship SoCs set to be launched in the second half of 2023. However, without access to EUV equipment, SMIC faces significant challenges in developing processes below 7nm, and even achieving mass production at 5nm is not a short-term goal.

As Qualcomm and MediaTek advance their products to 4nm and below, the Kirin series will likely remain constrained by SMIC’s process technology, making it difficult to significantly increase clock speeds and reduce power consumption. This situation will lead to a gradual widening of the performance gap between the Kirin series and Snapdragon 8 Gen series, and the Dimensity series. As they grapple with the responsibility of technological advancement, maintaining a competitive performance gap for the Kirin series against other flagship SoCs will be a primary challenge for Huawei and SMIC moving forward.

(Photo credit: Huawei)

According to Taiwan’s TechNews report, Lu Donghui, Chairman of Micron Technology Taiwan, stated that in response to the growing demand in the AI market, Micron Technology Taiwan will continue to invest in advanced processes and packaging technologies to produce High Bandwidth Memory (HBM) products. Micron Technology Taiwan is the only Micron facility globally with advanced packaging capabilities.

Lu Donghui, speaking at a media event, mentioned that Micron had previously introduced the industry’s first 8-layer stack (8-High) 24GB HBM3 Gen 2 product, which is now in the sampling phase. This product boasts a bandwidth exceeding 1.2TB/s and a transmission rate exceeding 9.2Gb/s, which is 50% higher than other HBM3 solutions on the market. Micron’s HBM3 Gen 2 product offers 2.5 times better energy efficiency per watt compared to previous generations, making it ideal for high-performance AI applications.

Micron’s HBM3 Gen 2 memory products are manufactured using the most advanced 1-beta process technology in Taiwan and Japan. Compared to the previous 1-alpha process, the 1-beta process reduces power consumption by approximately 15% and increases bit density by over 35%, with each chip offering a capacity of up to 16Gb. Through Micron’s advanced packaging technology, the 1-beta process memory chips are stacked in 8 layers, and the complete HBM3 Gen 2 chips are packaged and sent to customers’ specified semiconductor foundries like TSMC, Intel, Samsung, or third-party packaging and testing facilities for GPUs, CPUs.

Lu Donghui highlighted that Taiwan’s robust semiconductor manufacturing ecosystem makes it the exclusive hub for Micron’s advanced packaging development worldwide. By combining this ecosystem with Micron’s offerings, they can provide customers with comprehensive solutions to meet market demands. While HBM products represent a relatively small portion of the overall memory market, their future growth potential is significant, with expectations to capture around 10% of the entire memory market in the short term.

(Photo credit: Micron)

According to Taiwan’s TechNews report, Chiang Shang-yi, former TSMC Co-COO and current Chief Semiconductor Strategist at Foxconn, shared insights during a Taiwan Television interview. He discussed his past role at TSMC, the potential impact of U.S. export restrictions on China’s semiconductor development, and revealed previously undisclosed stories. Chiang emphasized the need to reevaluate China’s approach to semiconductor manufacturing.

Chiang previously stated that he wouldn’t return to China, and when asked about geopolitical challenges in the region due to U.S. chip restrictions, he shared his experiences in China.

He mentioned that his initial focus was primarily on research and development, and while technical challenges were manageable, the most significant challenge was related to human interactions. Chiang also disclosed two instances where he experienced a lack of trust from Chinese authorities.

He explained that the headquarters of SMIC is in Shanghai, with its largest facility located in Beijing. On two separate occasions, senior executives were scheduled to visit the Beijing facility, and Chiang was instructed to participate. However, he was informed just a day prior that he, as a non-Chinese national, would not be allowed to attend these visits. Similar incidents occurred twice, leaving him with a rather uncomfortable impression.

Regarding the U.S. chip ban, Chiang acknowledged that China had invested heavily in semiconductors over the past decade, and the recent restrictions were a more recent development. However, he emphasized that even before the restrictions, China’s semiconductor industry faced challenges and that the way China pursued semiconductor development needed reevaluation.

On the other hand, Chiang discussed why TSMC has been successful, attributing it to its business model and rapid decision-making. He mentioned a proposal he made to establish a packaging unit within TSMC to address the bottleneck created by the end of Moore’s Law. This proposal, referred to as “Advanced Packaging,” was quickly approved by TSMC’s founder, Morris Chang, who provided the resources to make it happen. This initiative led to the development of CoWoS (Chip-on-Wafer-on-Substrate) technology.

However, despite the innovation, CoWoS initially faced challenges gaining business traction and was even considered a joke within the company. Chiang had to work hard to promote the technology to customers. During a dinner with a Qualcomm executive, Chiang learned that CoWoS’s price was too high for consideration, with the executive requiring a price reduction to one cent per minimeter square. Chiang returned to TSMC and urged R&D to lower costs while maintaining performance, eventually leading to the success of InFO (Integrated Fan-Out) technology.

Chiang mentioned that the first customer to embrace CoWoS technology was Huawei, primarily for GPU chips, well before AI applications gained prominence. He humorously credited the Qualcomm executive for saving him with a single sentence and emphasized that innovation needed to be practical, not just technological, to succeed in the industry.